EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 48

• Manufacturer Part Number: EVAL-ADUC7128QSPZ
• Description: KIT DEV FOR ADUC7128
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7128QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7128
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7128/ADuC7129
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON, described in Table 57.
Table 57. CMPCON MMR Bit Designations
Bit
15:11
10
9:8
7:6
5
4:3
2
1
0
Value
00
01
10
11
00
01
10
11
00
01
10
11
Name
CMPEN
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
Description
Reserved.
Comparator Enable Bit.
Note: A comparator interrupt is generated on the enable of the comparator. This should be cleared in the
user software.
Comparator Negative Input Select Bits.
AVDD/2.
ADC3 input.
V
Reserved.
Comparator Output Configuration Bits.
IRQ and PLA connections disabled.
IRQ and PLA connections disabled.
PLA connections enabled.
IRQ connections enabled.
Comparator Output Logic State Bit.
Response Time.
5 μs response time typical for large signals (2.5 V differential).
17 μs response time typical for small signals (0.65 mV differential).
Reserved.
Reserved.
3 μs response time typical for any signal type.
Comparator Hysteresis Bit.
Comparator Output Rising Edge Interrupt.
Comparator Output Falling Edge Interrupt.
REF
When low, the comparator output is high when the positive input (CMP0) is above the negative
input (CMP1).
When high, the comparator output is high when the positive input is below the negative input.
Set by user to have a hysteresis of about 7.5 mV.
Cleared by user to have no hysteresis.
Set automatically when a rising edge occurs on the monitored voltage (CMP0).
Cleared by user by writing a 1 to this bit.
Set automatically when a falling edge occurs on the monitored voltage (CMP0).
Cleared by user.
Set by user to enable the comparator.
Cleared by user to disable the comparator.
× 0.6.
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