OM11014 NXP Semiconductors, OM11014 Datasheet - Page 23

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
LPC2917_19_1
Product data sheet
8.4.2.1 Overview
8.4.2.2 Description
8.4.2.3 Pin description
8.4.2.4 Watchdog timer clock description
8.4.2 Watchdog timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
watchdog timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the watchdog timer control register is set.
The Watchdog Reset output is fed to the Reset Generation Unit (RGU). The RGU
contains a reset source register to identify the reset source when the device has gone
through a reset. See
The watchdog has no external pins.
The watchdog timer is clocked by two different clocks; CLK_SYS_PESS and CLK_SAFE,
see
CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which is
always on.
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CLK_UART0/1
CLK_SPI0/1/2
CLK_TMR0/1/2/3
CLK_SAFE see
Internal chip reset if not periodically triggered
Timer counter register runs on always-on safe clock
Optional interrupt generation on watchdog time-out
Debug mode with disabling of reset
Watchdog control register change-protected with key
Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
Section
7.2.2. The register interface towards the system bus is clocked by
Section 7.2.2
Section
Rev. 01 — 31 July 2008
8.8.5.
ARM9 microcontroller with CAN and LIN
LPC2917/19
© NXP B.V. 2008. All rights reserved.
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