EVAL-ADUC847QSZ Analog Devices Inc, EVAL-ADUC847QSZ Datasheet - Page 8
EVAL-ADUC847QSZ
Manufacturer Part Number
EVAL-ADUC847QSZ
Description
KIT DEV QUICK START FOR ADUC847
Manufacturer
Analog Devices Inc
Series
QuickStart™ Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC845QSZ.pdf
(108 pages)
Specifications of EVAL-ADUC847QSZ
Contents
Evaluation Board, Power Supply, Cable, Software and Documentation
Silicon Manufacturer
Analog Devices
Core Architecture
8051
Silicon Core Number
ADuC847
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
ADUC8xx
Development Tool Type
Hardware - Eval/Demo Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC847
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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- Download datasheet (2Mb)
ADuC845/ADuC847/ADuC848
Parameter
LOGIC OUTPUTS
(All Digital Outputs except XTAL2)
START-UP TIME
FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS
POWER REQUIREMENTS
V
V
Floating State Leakage Current
Floating State Output Capacitance
From Power-Down Mode
Endurance
Data Retention
Power Supply Voltages
5 V Power Consumption
At Power-On
After Ext RESET in Normal Mode
After WDT RESET in Normal Mode
Typical Additional Peripheral
Currents (AI
OH
OL
Oscillator Running
Oscillator Powered Down
AV
AV
DV
DV
Normal Mode
Power-Down Mode
Primary ADC
Auxiliary ADC (ADuC845 Only)
Power Supply Monitor
DAC
Dual Excitation Current Sources
ALE Off
WDT
Footnotes at end of table.
, Output Low Voltage
, Output High Voltage
Wake-Up with INT0 Interrupt
Wake-Up with SPI Interrupt
Wake-Up with TIC Interrupt
Wake-Up with INT0 Interrupt
Wake-Up with SPI Interrupt
DV
AV
DV
AV
DD
DD
DD
DD
3 V Nominal
5 V Nominal
DD
DD
DD
DD
3 V Nominal
5 V Nominal
Current
Current
Current
Current
9
DD
and DI
10
11, 12
DD
11, 12
)
2
2
Min
2.4
2.4
100,000
100
2.7
4.75
2.7
4.75
Typ
10
600
3
2
20
20
20
30
30
25
40
50
20
30
30
60
−20
10
1
0.5
200
Rev. B | Page 8 of 108
Max
0.4
0.4
±10
3.6
5.25
3.6
5.25
10
31
180
53
33
1
3
Unit
V
V
V
V
µA
pF
ms
ms
ms
µs
µs
µs
µs
µs
Cycles
Years
V
V
V
V
mA
mA
µA
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
µA
µA
µA
Conditions
DV
DV
I
I
Controlled via WDCON SFR
PLLCON.7 = 0
4.75 V < DV
Core clock = 1.57 MHz
Core clock = 12.58 MHz
T
T
T
T
T
T
5 V V
DACH/L = 000H
200 µA each. Can be combined to give 400 µA on
PCON.4 = 1 (see Table 6)
PLLCON.7 = 1
SINK
SINK
MAX
MAX
MAX
MAX
MAX
MAX
a single output.
DD
DD
= 8 mA, SCLOCK, SDATA
= 1.6 mA on P0, P1, P2
= 85°C; OSC on; TIC on
= 125°C; OSC on; TIC on
= 85°C; OSC off
= 125°C; OSC off
= 85°C; OSC on or off
= 125°C; OSC on or off
DD
= 5 V, I
= 3 V, I
, CD = 3
DD
SOURCE
SOURCE
< 5.25 V, AV
= 80 µA
= 20 µA
DD
= 5.25 V
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