C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 76
![DEVKIT-F120/21/22/23/24/25/26/27](/photos/9/20/92070/c8051f120dk_sml.jpg)
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
- Current page: 76 of 350
- Download datasheet (2Mb)
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
6.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR0 signal is used to initiate
conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on
the rising edge of CNVSTR0 (see Figure 6.3). Tracking can also be disabled (shutdown) when the entire
chip is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see
“6.2.3. Settling Time Requirements” on page 77
76
Timer 2, Timer 3 Overflow;
(AD0CM[1:0]=00, 01, 11)
Write '1' to AD0BUSY
(AD0CM[1:0]=10)
SAR Clocks
SAR Clocks
SAR Clocks
ADC0TM=1
ADC0TM=0
ADC0TM=1
ADC0TM=0
CNVSTR0
Figure 6.3. ADC0 Track and Conversion Example Timing
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
Low Power
Low Power
or Convert
or Convert
Track or
Convert
Track Or Convert
1
1
Track
2
2
Track
3
3
4
4
1
5
5
2
6
6
3
7
7
Rev. 1.4
Convert
).
4
8
8
5
9
9
10 11 12 13 14 15 16 17 18 19
10 11 12 13 14 15 16
6
Convert
7
Convert
Convert
8
9
10 11 12 13 14 15 16
Low Power Mode
Track
Low Power Mode
Track
Section
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