C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 311
![DEVKIT-F120/21/22/23/24/25/26/27](/photos/9/20/92070/c8051f120dk_sml.jpg)
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
- Current page: 311 of 350
- Download datasheet (2Mb)
23.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
23.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 or Timer 1 to operate as 8-bit counter/timers with automatic reload of the start
value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF
to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer
0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not
changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be cor-
rect. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0
is low
.
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
GATE0
Figure 23.2. T0 Mode 2 Block Diagram
0
1
TR0
CKCON
M
T
1
0
1
M
T
0
C
S
A
1
Rev. 1.4
C
S
A
0
G
A
T
E
1
C
T
1
/
M
T
C8051F120/1/2/3/4/5/6/7
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
C8051F130/1/2/3
Reload
TR1
TR0
TF1
TF0
IE1
IT1
IE0
IT0
Interrupt
311
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