C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 226
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
226
Bits7–6: EAS1–0: EMIF Address Setup Time Bits.
Bits5–2: EWR3–0: EMIF /WR and /RD Pulse-Width Control Bits.
Bits1–0: EAH1–0: EMIF Address Hold Time Bits.
EAS1
R/W
Bit7
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
0000: /WR and /RD pulse width = 1 SYSCLK cycle.
0001: /WR and /RD pulse width = 2 SYSCLK cycles.
0010: /WR and /RD pulse width = 3 SYSCLK cycles.
0011: /WR and /RD pulse width = 4 SYSCLK cycles.
0100: /WR and /RD pulse width = 5 SYSCLK cycles.
0101: /WR and /RD pulse width = 6 SYSCLK cycles.
0110: /WR and /RD pulse width = 7 SYSCLK cycles.
0111: /WR and /RD pulse width = 8 SYSCLK cycles.
1000: /WR and /RD pulse width = 9 SYSCLK cycles.
1001: /WR and /RD pulse width = 10 SYSCLK cycles.
1010: /WR and /RD pulse width = 11 SYSCLK cycles.
1011: /WR and /RD pulse width = 12 SYSCLK cycles.
1100: /WR and /RD pulse width = 13 SYSCLK cycles.
1101: /WR and /RD pulse width = 14 SYSCLK cycles.
1110: /WR and /RD pulse width = 15 SYSCLK cycles.
1111: /WR and /RD pulse width = 16 SYSCLK cycles.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
SFR Definition 17.3. EMI0TC: External Memory Timing Control
EAS0
R/W
Bit6
ERW3
R/W
Bit5
EWR2
R/W
Bit4
Rev. 1.4
EWR1
R/W
Bit3
EWR0
R/W
Bit2
EAH1
R/W
Bit1
SFR Address:
SFR Page:
EAH0
R/W
Bit0
0xA1
0
Reset Value
11111111
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