C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 271
![DEVKIT-F120/21/22/23/24/25/26/27](/photos/9/20/92070/c8051f120dk_sml.jpg)
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
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Mode
Status
Code
0xA0
0xA8
0xB0
0xB8
0xC0
0xC8
0xD0
0xF8
0x60
0x68
0x70
0x78
0x80
0x88
0x90
0x98
0x00
Table 19.1. SMB0STA Status Codes and States (Continued)
Own slave address + W received. ACK trans-
mitted.
Arbitration lost in sending SLA + R/W as mas-
ter. Own address + W received. ACK transmit-
ted.
General call address received. ACK transmit-
ted.
Arbitration lost in sending SLA + R/W as mas-
ter. General call address received. ACK trans-
mitted.
Data byte received. ACK transmitted.
Data byte received. NACK transmitted.
Data byte received after general call address.
ACK transmitted.
Data byte received after general call address.
NACK transmitted.
STOP or repeated START received.
Own address + R received. ACK transmitted.
Arbitration lost in transmitting SLA + R/W as
master. Own address + R received. ACK
transmitted.
Data byte transmitted. ACK received.
Data byte transmitted. NACK received.
Last data byte transmitted (AA=0). ACK
received.
SCL Clock High Timer per SMB0CR timed out
Bus Error (illegal START or STOP)
Idle
SMBus State
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Wait for data.
Save current data for retry when bus is
free. Wait for data.
Wait for data.
Save current data for retry when bus is
free.
Read SMB0DAT. Wait for next byte or
STOP.
Set STO to reset SMBus.
Read SMB0DAT. Wait for next byte or
STOP.
Set STO to reset SMBus.
No action necessary.
Load SMB0DAT with data to transmit.
Save current data for retry when bus is
free. Load SMB0DAT with data to trans-
mit.
Load SMB0DAT with data to transmit.
Wait for STOP.
Set STO to reset SMBus.
Set STO to reset SMBus.
Set STO to reset SMBus.
State does not set SI.
C8051F130/1/2/3
Typical Action
271
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