EVAL-AD7689EDZ Analog Devices Inc, EVAL-AD7689EDZ Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD7689EDZ
• Description: BOARD EVAL AD7689
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7689EDZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: ±VREF
• Power (typ) @ Conditions: 12.5mW @ 250kSPS, 5 V
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7689
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD7689
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC),
and read/write spanning conversion (RSC). Note that the gating
item for both CFG and data readback is at the end of conversion
(EOC). At EOC, if CNV is high, the busy indicator is disabled.
As detailed previously in the Digital Interface section, the data
access should occur up to safe data reading/writing time, t
If the full CFG word was not written to prior to EOC, it is dis-
carded and the current configuration remains. If the conversion
result is not read out fully prior to EOC, it is lost as the ADC
updates SDO with the MSB of the current conversion. For
detailed timing, refer to Figure 40 and Figure 41, which depict
reading/writing spanning conversion with all timing details,
including setup, hold, and SCK.
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS
RDC
RAC
RSC
REQUIRED TO RETURN SDO TO HIGH-Z.
PHASE
SDO
SCK
SDO
SCK
CNV
CNV
SDO
CNV
SCK
DIN
DIN
DIN
POWER
UP
MSB
XXX
(n – 2) UNDEFINED
1
CONVERSION
DATA (n – 3)
XXX
t
XXX
CONV
16
t
CYC
EOC
Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator
(n – 1) UNDEFINED
NOTE 1
NOTE 1
NOTE 1
ACQUISITION
1
1
DATA (n – 2)
DATA (n – 2)
CFG (n)
NOTE 2
CFG (n)
XXX
XXX
16
n
SOC
n + 1
(n – 1) UNDEFINED
DATA (n – 2)
CONVERSION
1
CFG (n)
t
NOTE 2
DATA (n – 2)
DATA
CFG (n)
XXX
NOTE 2
XXX
16
16
DATA
Rev. B | Page 25 of 32
EOC
.
ACQUISITION
1
1
CFG (n + 1)
DATA (n – 1)
CFG (n + 1)
DATA (n – 1)
(n)
XXX
XXX
MSB
XXX
16
n
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 37 with
SCK idling low.
From power-up, in any read/write mode, the first three conver-
sion results are undefined because a valid CFG does not take
place until the 2
required. Also, if the state machine writes the CFG during the
power-up state (RDC shown), the CFG register needs to be
rewritten again at the next phase. Note that the first valid data
occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
n + 1
CFG (n + 1)
DATA (n – 1)
CFG (n + 1)
1
CONVERSION
DATA (n – 1)
XXX
XXX
(n)
16
16
nd
EOC
EOC; thus two dummy conversions are
ACQUISITION
1
1
CFG (n + 2)
DATA (n)
CFG (n + 2)
(n + 1)
DATA (n)
16
MSB
n
(n)
n + 1
CFG (n + 2)
CONVERSION
1
CFG (n + 2)
DATA (n)
(n + 1)
DATA (n)
AD7682/AD7689
16
16
EOC
ACQUISITION
1
1
DATA (n + 1)
DATA (n + 1)
CFG (n + 3)
CFG (n + 3)
(n + 2)
(n + 1)
n
MSB