LMK04000BEVALXO National Semiconductor, LMK04000BEVALXO Datasheet - Page 25

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LMK04000BEVALXO

Manufacturer Part Number
LMK04000BEVALXO
Description
BOARD EVAL PREC CLOCK PLL XO
Manufacturer
National Semiconductor
Series
PowerWise®r

Specifications of LMK04000BEVALXO

Main Purpose
Timing, Clock Conditioner
Embedded
No
Utilized Ic / Part
LMK04000
Primary Attributes
122.88 MHz Crystal
Secondary Attributes
Integrated PLL & VCO
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Appendix B: Typical Phase Noise Performance Plots
PLL1
The LMK040xxB’s two stage jitter cleaning process involves masking the reference noise with a
VCXO or Crystal. Therefore the phase noise performance of the VCXO or Crystal of PLL1 is a
very important contributor to the final phase noise of the system.
Crystek 122.88 MHz VCXO
The phase noise of the reference is masked by the phase noise of this VCXO by using a narrow
loop bandwidth. This VCXO sets the reference noise to PLL2. Figure 13 shows the open loop
typical phase noise performance of the CVHD-950-122.88 Crystek VCXO.
Figure 13 - CVHD-950-122.88 MHz VCXO Phase Noise at 122.88 MHz
-100
-110
-120
-130
-140
-150
-160
-170
-50
-60
-70
-80
-90
Table 6 - VCXO Phase Noise
10
at 122.88 MHz (dBc/Hz)
100 kHz
Offset
10 MHz
40 MHz
100 Hz
10 kHz
1 MHz
10 Hz
L M K 0 4 0 X X - R E V 3
1 kHz
100
Phase
-108.9
-137.4
-153.3
-162.0
-165.7
-168.1
-168.1
Noise
-76.6
1000
VCXO Phase Noise
E V A L U A T I O N
10000
Offset (Hz)
25
100000
B O A R D
O P E R A T I N G
Table 7 - VCXO RMS Jitter
1000000 10000000
to high offset of 20 MHz
at 122.88 MHz (rms fs)
100 kHz
Offset
10 MHz
100 Hz
10 kHz
Low
1 MHz
10 Hz
1 kHz
CVHD-950-122.88
I N S T R U C T I O N S
515.4
Jitter
60.5
36.2
35.0
34.5
32.9
22.7
1E+08

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