LMK04000BEVALXO National Semiconductor, LMK04000BEVALXO Datasheet - Page 23

• Manufacturer Part Number: LMK04000BEVALXO
• Description: BOARD EVAL PREC CLOCK PLL XO
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVALXO

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz Crystal
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

• CLKin Options Box
• PLL2_LF Box
• CLKout Options Box
• CLKout CMOS Options Box
• VCO Control – FC Box
• Program Pins Box
o CLKin_SEL – Sets manual or automatic switching modes for selecting a
o LOS_TIMEOUT – The timeout value before a loss of signal on a clock input is
o LOS_TYPE – Set the type of output for the LOS pins.
o CLKin0_BUFTYPE & CLKin1_BUFTYPE – Select the input buffer used for the
o Set the integrated loop filter values for PLL2 including,
o It is also possible to set these values by clicking on the loop filter values on the
o EN_CLKout_Global – A global enable for clocks, if unchecked no outputs will
o EN_CLKout0 through EN_CLKout4 – Individual clock output enables. These
o The number of options vary depending on the option of the LMK device selected.
o The presence of this box and the number of options on this tab depends upon the
o OSCin_FREQ – Must be set to the reference frequency of PLL2 in MHz, which
o GOE – Set high or low voltage on GOE pin. Checked is high voltage.
o SYNC* – Set high or low voltage on SYNC* pin. Checked is high voltage.
o TRIGGER – Set high or low voltage on pin 10 of uWire header.
reference oscillator for PLL1.
registered on the LOS pins.
respective clock input.
Clock Outputs tab.
be observed!
can also be set on the Clock Outputs tab.
option of the LMK device.
should normally be the VCO frequency of PLL1. NOTE: It is important to
enter the correct frequency value in this field, as it is used by the internal
state machine of the LMK040xxB to execute its calibration routine for the
internal VCO. An incorrect value may result in an unlocked condition for the
synthesizer.
L M K 0 4 0 X X - R E V 3
PLL2_R3_LF – R3 value
PLL2_R4_LF – R4 value
PLL2_C3_C4_LF – C3 and C4 value at the same time
CLKout#_PECL_LVL – Set the level of an LVPECL output to LVPECL
or 2VPECL. The 2VPECL a higher output level than LVPECL.
CLKout##_STATE – Set the state of the individual LVCMOS output.
Entering a reference oscillator frequency on PLL2 tab will automatically
update this register with the frequency to the nearest MHz.
If GOE is low, then no clock outputs will be observed!
If SYNC* is low, then no clock outputs will be observed on divided clock
outputs!
E V A L U A T I O N
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O P E R A T I N G
I N S T R U C T I O N S