LMK04000BEVALXO National Semiconductor, LMK04000BEVALXO Datasheet - Page 11

• Manufacturer Part Number: LMK04000BEVALXO
• Description: BOARD EVAL PREC CLOCK PLL XO
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVALXO

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz Crystal
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7. Enable Clock Outputs
To measure phase noise at the clock outputs,
Figure 6 - Setting Divide, Delay, CLKout_MUX, Enabled for CLKout1 on "Clock Outputs" tab.
See Appendix B: Typical Phase Noise Performance Plots for phase noise plots of the clock
outputs.
National’s Clock Design Tool can be used to calculate divider values to achieve desired clock
output frequencies. See: http://www.national.com/timing/software/.
1. Click on the “Clock Outputs” tab,
2. Enable an output,
3. Then set the
4. Connect the clock output SMAs to a spectrum analyzer or signal source analyzer.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
a. CLKout MUX mode,
b. divide value, and
c. delay value.
a. For LVDS, a balun is recommended such as the ADT2-1T.
b. For LVPECL,
c. For LVCMOS,
L M K 0 4 0 X X - R E V 3
iii. A balun may be used. Ensure CLKout_#a and
ii. One side of the LVPECL signal can be terminated with a 50 ohm load and
ii. One side of the LVCMOS signal can be terminated
i. A balun can be used, or
i. Only one side of the LVCMOS signal can be turned
the other side can be run to the test equipment single ended.
on by setting the CLKout_#a / CLKout_#b states in
the CLKout CMOS Options on the Bits/Pins tab.
with a 50 ohm load and the other side can be run to
the test equipment single ended.
CLKout_#b states are complementary, for example:
Non-inverted and Inverted.
E V A L U A T I O N
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B O A R D
O P E R A T I N G
I N S T R U C T I O N S
Figure 7 - Setting
LVCMOS modes.