lmk04000b National Semiconductor Corporation, lmk04000b Datasheet
lmk04000b
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lmk04000b Summary of contents
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... CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence. PLLatinum ™ trademark of National Semiconductor Corporation. TRI-STATE ® registered trademark of National Semiconductor Corporation. ...
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... LMK04010BISQ BiCMOS LMK04011BISQ BiCMOS LMK04031BISQ BiCMOS LMK04033BISQ BiCMOS NSID CLKout0 LMK04000BISQ 2VPECL / LVPECL LMK04001BISQ 2VPECL / LVPECL LMK04002BISQ 2VPECL / LVPECL LMK04010BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL LMK04011BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL ...
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Functional Block Diagram 3 30027101 www.national.com ...
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General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Target Applications .......................................................................................................................... 1 4.0 Functional Block Diagram ................................................................................................................. 3 5.0 Connection Diagram ........................................................................................................................ 6 6.0 Pin Descriptions ............................................................................................................................. 7 7.0 Absolute Maximum Ratings .............................................................................................................. 9 8.0 Package Thermal Resistance ...
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PLL1_N: PLL1_N Counter ........................................................................................... 35 16.9.2 PLL1_R: PLL1_R Counter ........................................................................................... 36 16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL) ................................................................................................................ 36 16.10 REGISTER 13 .................................................................................................................... 36 16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ......................................................... 36 16.10.2 EN_Fout: ...
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Connection Diagram www.national.com 48-Pin LLP Package 6 30027102 ...
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Pin Descriptions Pin Number Name(s) 1 GND 2 Fout CLKuWire 5 DATAuWire 6 LEuWire LDObyp1 10 LDObyp2 11 GOE CLKout0 ...
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Pin Number Name(s) 41 CLKout2 42 CLKout2 CLKout3 45 CLKout3 CLKout4 48 CLKout4* DAP DAP Note 2: The reference clock inputs may be either coupled. www.national.com I/O ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Supply Voltage (Note 6) Input Voltage Storage Temperature Range Lead Temperature (solder 4 sec) Differential Input Current ...
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Electrical Characteristics ≤ ≤ ≤ (3. 3.45 V, -40 ° the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol I Power Down Supply Current CC_PD Supply Current with ...
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Symbol Parameter PLL1 Phase Detector f PD Frequency PLL1 Charge Pump Source I SOURCE CPout1 Current (Note 12) PLL1 Charge Pump Sink I SINK CPout1 Current (Note 12) Charge Pump Sink / Source I %MIS CPout1 Mismatch Magnitude of Charge ...
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Symbol f Crystal Frequency Range XTAL Crystal Effective Series ESR Crystal Power Dissipation P XTAL Input Capacitance LMK040xx OSCin port PLL2 Phase Detector and Charge Pump Specifications f Phase Detector Frequency PD PLL2 Charge Pump Source I ...
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Symbol Parameter f VCO Tuning Range VCO VCO Output power VCO 50 Ω load driven by Fout Fine Tuning Sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at K the lower ...
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Symbol f VCO SSB Phase Noise PLL2 = Open Loop Measured at Fout f VCO SSB Phase Noise PLL2 = Open Loop Measured at Fout f VCO SSB Phase Noise PLL2 = Open Loop Measured at Fout f VCO SSB ...
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Symbol Parameter Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO LMK040x0 (Note 19 1200 MHz VCO SSB Phase Noise PLL2 = Closed Loop Measured at Fout LMK040x1 (Note 20 1500 ...
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Symbol CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO LMK040x0 (Note 23) f CLKout SSB Phase Noise Measured at Clock Outputs Value is average for all output LMK040x1 (Note 24) f CLKout SSB ...
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Symbol Parameter CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO LMK040x0 (Notes 27, 31 250 MHz CLKout Integrated RMS Jitter LMK040x1 (Notes 28, 31 250 MHz CLKout Integrated RMS Jitter J CLKout ...
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Symbol CLKout's Internal VCO Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit LMK040x0 (Note 32) f CLKout Integrated RMS Jitter LMK040x1 (Note 33) f CLKout Integrated RMS Jitter J CLKout LVPECL/2VPECL/LVDS LMK040x2 (Note 34) f CLKout ...
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Symbol Parameter Default Power On Reset Clock Output Frequency Default output clock frequency f CLKout-startup at device power on Maximum Frequency f CLKout (Note 36) CLKoutX to CLKoutY T SKEW (Note 37) V Differential Output Voltage OD Change in Magnitude ...
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Symbol f Maximum Frequency CLKout V Output High Voltage OH V Output Low Voltage OL I Output High Current (Source Output Low Current (Sink) OL Skew between any two T LVCMOS outputs, same SKEW channel or different channel ...
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Note 19: For LMK040x0 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO VCO_DIV = 100 ...
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Serial Data Timing Diagram Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the register is sent from the ...
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Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. 12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT VOLTAGE 12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT ...
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Typical Performance Characteristics 13.1 CLOCK OUTPUT AC CHARACTERISTICS LVDS VOD vs. Frequency LVCMOS Vpp vs. Frequency Clock Channel Delay Noise Floor vs. Frequency (Note 41) Note 40: To estimate this noise, only the output frequency is required. Divide value ...
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Clock Output AC Characteristics (continued) Typical LVDS Phase Noise, F Typical LVPECL Phase Noise, F Typical LVCMOS Phase Noise, F Note 42: Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 µA, PLL1 Loop ...
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Features 14.1 SYSTEM ARCHITECTURE The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in ...
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The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled automatically if the synthesizer is not locked. See Section 16.3.2 EN_CLKoutX: Clock Channel Output Enable in Functional Description for actual implementation ...
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Digital Lock Detect 1 Bypass The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate the in- ternal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must ...
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General Programming Information LMK040xx devices are programmed using several 32-bit reg- isters. Each register consists of a 4-bit address field and 28- bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data ...
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EN_CLKout0 CLKout0_PECL_LVL Register www.national.com EN_CLKout1 EN_CLKout2 CLKout1A_STATE [1:0] CLKout2A_STATE [1:0] CLKout1B_STATE [1:0] CLKout2B_STATE [1:0] CLKout1_PECL_LVL CLKout2_PECL_LVL 30 EN_CLKout3 EN_CLKout4 CLKout3A_STATE [1:0] CLKout3B_STATE [1:0] CLKout4_PECL CLKout3_PECL_LVL _LVL ...
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RESET RC_DLD1_Start Register CLKin_SEL [1:0] PLL2_C3_C4_LF [3:0] LOS_TYPE [1:0] LOS_TIMEOUT [1:0] CLKin0_BUFTYPE CLKin1_BUFTYPE PLL1 CP TRI-STATE PLL2 CP TRI-STATE EN_CLKout_Global, PLL1_CP_POL 31 PLL2_R3_LF [2:0] PLL2_R4_LF [2:0] EN_PLL2_REF2X POWER DOWN, default = 0 default=1 EN_Fout EN_PLL2_XTAL www.national.com ...
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DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET Table 2 illustrates the default register settings programmed in silicon for the LMK040xx after power on or asserting the reset bit. TABLE 2. Default Device Register Settings after Power On/Reset Field Name ...
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REGISTER Registers R0 through R4 control the five clock outputs. Reg- ister R0 controls CLKout0, Register R1 controls CLKout1, and so on. Aside from this, the functions of the bits in these reg- isters are identical. ...
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CLKoutX/CLKoutX* LVPECL Mode Control Clock outputs designated as LVPECL can be configured in one of two possible output levels. The default mode is the common LVPECL swing of 800 mVp-p single-ended (1.6 Vp- p differential). A second mode, 2VPECL, ...
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CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits This register allows the user to set the reference clock input that is used to lock PLL1 select an auto-switching mode. The automatic switching modes are revertive ...
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PLL1_R: PLL1_R Counter The size of the PLL1_R counter is 12 bits. This counter will support a maximum divide ratio of 4095 and minimum divide ratio of 1. TABLE 15. PLL1_R Counter Values R [11:0] b11 b10 b9 b8 ...
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TABLE 20. PLL2 Internal Loop Filter Resistor Values, PLL2_R3_LF PLL2_R3_LF [2: TABLE 21. ...
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TABLE 27. PLL_MUX: LD Pin Selectable Outputs PLL_MUX [4:0] LD Output PLL2 Digital Lock Detect ...
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Application Information 17.1 SYSTEM LEVEL DIAGRAM The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application. FIGURE 3. Typical Application 39 30027170 www.national.com ...
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System Level Diagram (continued) Figure 3 shows an LMK04000 family device with external cir- cuitry. The primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential drivers. ...
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FIGURE 4. Loop Filter 41 30027171 www.national.com ...
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TABLE 31. Typical Current Consumption for Selected Functional Blocks Block Condition Single input clock (CLKIN_SEL = 0 or 1); LOS Entire device, disabled; PLL1 and PLL2 locked; All CLKouts are off; core current No LVPECL emitter resistors connected REFMUX Enable ...
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CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following ta- ble serves to provide enough information to allow the user to calculate estimated current consumption of the device. Un- less otherwise noted V ...
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FIGURE 6. Reference Design Circuit for Crystal Oscillator Option 17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) The LMK04000 family features supporting circuitry for a dis- cretely implemented oscillator driving the OSCin port pins. Figure 6 illustrates a reference design circuit for ...
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C = Load capacitance Shunt capacitance of the crystal, specified on the crystal 0 datasheet The endpoints of the circuit’s load capacitance L1 L2 range, assuming a variable capacitance element is one com- ...
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Example crystal specifications are presented in Table 33. Parameter Nominal Frequency (MHz) Frequency Stability °C Operating temperature range Frequency Stability, -40 °C to +85 °C Load Capacitance Shunt Capacitance (C Motional Capacitance (C Equivalent Series Resistance Drive ...
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F is the nominal frequency of the crystal and is in units of NOM MHz. Using the data, this becomes: In order to ensure startup of the oscillator circuit, the equiva- lent series resistance (ESR) of the selected crystal should ...
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FIGURE 11. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver Some LVDS receivers may effectively have internal biasing on the inputs. In this case, the circuit shown in Figure 11 is modified by replacing the 50 Ω terminations ...
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DRIVING CLKin AND OSCin INPUTS 17.9.1 Driving CLKin Pins with a Differential Source Both CLKin ports can be driven by differential signals recommended that the input mode be set to bipolar (CLKinX_TYPE = 0) when using differential ...
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Figure 22 compares the phase noise of two different VCXOs: VCXO “A” and VCXO “B”. Both VCXOs have a center fre- quency of 100 MHz. The figure of merit, RMS jitter, is mea- This plot shows that VCXO “B” exhibits ...
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FIGURE 23. LVDS Clock Output Phase Noise Comparison, 250 MHz FIGURE 24. LVPECL Clock Output Phase Noise Comparison, 250 MHz FIGURE 25. LVCMOS Clock Output Phase Noise Comparison, 250 MHz 51 30027150 30027151 30027152 www.national.com ...
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... Physical Dimensions 19.0 Ordering Information VCO Frequency Order Number Band LMK04000BISQX 1.2 GHz LMK04000BISQ 1.2 GHz LMK04000BISQE 1.2 GHz LMK04001BISQX 1.5 GHz LMK04001BISQ 1.5 GHz LMK04001BISQE 1.5 GHz LMK04002BISQX 1.6 GHz LMK04002BISQ 1.6 GHz LMK04002BISQE 1.6 GHz LMK04010BISQX 1.2 GHz LMK04010BISQ 1.2 GHz LMK04010BISQE 1.2 GHz LMK04011BISQX 1.5 GHz LMK04011BISQ 1.5 GHz LMK04011BISQE 1.5 GHz LMK04031BISQX 1.5 GHz LMK04031BISQ 1 ...
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