CDB5376 Cirrus Logic Inc, CDB5376 Datasheet

EVALUATION BOARD FOR CS5376

CDB5376

Manufacturer Part Number
CDB5376
Description
EVALUATION BOARD FOR CS5376
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB5376

Main Purpose
Seismic Evaluation System
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
CS3301A, CS3302A, CS4373A, CS5372A, CS5376A
Primary Attributes
Quad Digital Filter
Secondary Attributes
Graphical User Interface, SPI™ & USB Interfaces
Processor To Be Evaluated
CS330x, CS4373A, CS537x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1778
Features
http://www.cirrus.com
Digital ∆Σ Input from CS5376A Digital Filter
Selectable Differential Analog Outputs
Multiple AC and DC Operational Modes
Selectable Attenuation for
Outstanding Performance
Low Power Consumption
Extremely Small Footprint
Bipolar Power Supply Configuration
• Precision output (
• Buffered output (
• Signal bandwidth: DC to 100 Hz
• Max AC amplitude: 5 V
• Max DC amplitude: + 2.5 V
• 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
• AC (OUT): -116 dB THD typical, -112 dB max
• AC (BUF): -108 dB THD typical, -90 dB max
• DC absolute accuracy: 0.4% typical, 1% max
• AC modes / DC modes: 40 mW / 20 mW
• Sleep mode / Power Down: 1 mW / 10 µW
• 28-pin SSOP package, 8 mm x 10 mm
• VA+ = +2.5 V;VA- = -2.5 V; VD = +3.3 V
Low-power, High-performance
TDATA
VREF+
VREF-
BUF±
OUT±
) for sensor tests
) for electronics tests
PP
VA+
VA-
CS3301A / CS3302A
differential
dc
differential
MODE(0, 1, 2)
CAP+ CAP-
24-Bit ∆Σ
Copyright © Cirrus Logic, Inc. 2006
DAC
(All Rights Reserved)
ATT(0, 1, 2)
Description
The CS4373A is a high-performance, differential output
digital-to-analog converter (DAC) with programmable at-
tenuation and multiple operational modes. AC test
modes measure system dynamic performance through
THD and CMRR tests while DC test modes are for gain
calibration and pulse tests.
The CS4373A is driven by a ∆Σ digital bit stream from the
CS5376A digital filter test bit stream (TBS) generator. It
has two sets of differential analog outputs, OUT and
BUF, to simplify system design as dedicated outputs for
testing the electronics channel and for in-circuit sensor
tests. Analog output attenuation is selected by simple pin
settings
CS3301A / CS3302A differential amplifiers for full-scale
testing at all gain ranges.
The CS4373A test DAC provides self-test and precision
calibration capability for high-resolution, low-frequency
multi-channel measurement systems designed from
CS3301A / CS3302A
CS5371A / CS5372A ∆Σ modulators and the CS5376A
digital filter.
ORDERING INFORMATION
Attenuator
See
Generator
Clock
page
and
34.
∆Σ
matches
GND
VD
Test DAC
OUT+
OUT-
BUF+
BUF-
MCLK
MSYNC
differential
the
CS4373A
gain
amplifiers,
DS699F2
of
DEC ‘06
the

Related parts for CDB5376

CDB5376 Summary of contents

Page 1

Low-power, High-performance Features Digital ∆Σ Input from CS5376A Digital Filter Selectable Differential Analog Outputs • Precision output ( ) for electronics tests OUT± • Buffered output ( ) for sensor tests BUF± Multiple AC and DC Operational Modes • Signal ...

Page 2

CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 2. GENERAL DESCRIPTION ..................................................................................................... 16 2.1 Digital Inputs .................................................................................................................... 16 2.2 Analog Outputs ................................................................................................................ 16 2.3 Multiple Operational Modes ............................................................................................. 16 2.4 Low Power ....................................................................................................................... 16 3. SYSTEM DIAGRAMS 4. POWER MODES ..................................................................................................................... 18 ...

Page 3

Figure 1. Digital Input Rise and Fall Times ................................................................................... 12 Figure 2. System Timing Diagram................................................................................................. 14 Figure 3. MCLK / MSYNC Timing Detail ....................................................................................... 14 Figure 4. CS4373A Block Diagram ............................................................................................... 16 Figure 6. Connection Diagram ...................................................................................................... 17 Figure 5. ...

Page 4

CHARACTERISTICS AND SPECIFICATIONS • Min / Max characteristics and specifications are guaranteed over the • Typical performance characteristics and specifications are measured at nominal supply voltages and T • GND = 0 V. Single-ended voltages with respect to GND, ...

Page 5

TEMPERATURE CONDITIONS Parameter Ambient Operating Temperature Storage Temperature Range Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-layer PCB) ABSOLUTE MAXIMUM RATINGS Parameter DC Power Supplies Analog Supply Differential Digital Supply Differential Input Current, Power Supplies Input Current, Any Pin ...

Page 6

ANALOG CHARACTERISTICS Parameter VREF Input {VREF+} - {VREF-} VREF- VREF Input Current, AC modes VREF Input Current, DC modes VREF Input Noise Analog OUT± Output ± Analog External Load at OUT (Note 7, 8) Differential Output Impedance Single-ended Output Impedance ...

Page 7

AC DIFFERENTIAL MODES Parameter AC Differential Characteristics Full-scale Differential AC Output Full-scale Bandwidth Impulse Amplitude AC Differential Accuracy Full-scale Accuracy (Note 3, 11) Relative Accuracy (Note 12) Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode ...

Page 8

AC DIFFERENTIAL MODES (CONT.) Parameter Signal to Noise Signal to Noise ± (OUT Unloaded) (Note 15) Signal to Noise ± (BUF Unloaded, 1 kΩ Load) (Note 15, 16) Total Harmonic Distortion Total Harmonic Distortion ± (OUT Unloaded) ...

Page 9

DC COMMON MODE 4 Parameter DC Common Mode Characteristics Common Mode Output Common Mode Drift DC Common Mode Accuracy Common Mode Match Noise ± Noise (OUT Unloaded) (Note 15) ± Noise (BUF Unloaded, 1 kΩ Load) (Note 15, 16) DS699F2 ...

Page 10

DC DIFFERENTIAL MODE 5 Parameter DC Differential Mode Characteristics Full-scale Differential DC Output (Note 19) DC Differential Accuracy Full-scale Accuracy (Note 3, 11) Relative Accuracy (Note 12) Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode Drift Noise ± ...

Page 11

AC COMMON MODE 6 Parameter AC Common Mode Characteristics Full-scale Common Mode AC Output (Note 20) Full-scale Bandwidth Impulse Amplitude AC Common Mode Accuracy ± Common Mode Match (OUT Unloaded) (Note 17, 20) ± Common Mode Match (BUF Unloaded, 1 ...

Page 12

DIGITAL CHARACTERISTICS Parameter Digital Inputs High-level Input Drive Voltage Low-level Input Drive Voltage Input Leakage Current Digital Input Capacitance Rise Times Except MCLK Fall Times Except MCLK TDATA Input TDATA Input Bit Rate TDATA Input One’s Density Range TBSGAIN Full-scale ...

Page 13

DIGITAL CHARACTERISTICS (CONT.) Parameter Master Clock MCLK Frequency MCLK Period MCLK Duty Cycle MCLK Rise Time MCLK Fall Time MCLK Jitter (In-band or aliased in-band) MCLK Jitter (Out-of-band) Master Sync MSYNC Setup Time to MCLK rising MSYNC Period MSYNC Hold ...

Page 14

DIGITAL CHARACTERISTICS (CONT.) SYNC MCLK (2.048 MHz) MSYNC t 0 TDATA (256 kHz) MCLK (2.048 MHz) t mss MSYNC TDATA (256 kHz) 14 Figure 2. System Timing Diagram t t msh mclk msync t tdata Figure 3. ...

Page 15

POWER SUPPLY CHARACTERISTICS Parameter AC Mode Supply Current (MODE = Analog Power Supply Current Digital Power Supply Current DC Mode Supply Current (MODE = 4) Analog Power Supply Current Digital Power Supply Current DC Mode Supply ...

Page 16

TDATA VREF+ VREF- 2. GENERAL DESCRIPTION The CS4373A is a differential output digital-to- analog converter with multiple operational modes and programmable output attenuation. It provides self-test and precision calibration capability for high-resolution, low-frequency measurement systems CS3301A / CS3302A differential amplifiers, ...

Page 17

SYSTEM DIAGRAMS Geophone or Hydrophone Sensor Geophone or Hydrophone Sensor Geophone or Hydrophone Sensor Geophone or Hydrophone Sensor SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ 2.5 V VREF VA- DS699F2 CS3301A CS3302A M ...

Page 18

POWER MODES The CS4373A has four power modes. AC test modes and DC test modes are operational modes, while the power down and sleep modes are non-operational, standby modes. 4.1 Power Down If MCLK is stopped, an internal loss-of-clock ...

Page 19

OPERATIONAL MODES The CS4373A has six operational modes and two sleep modes selected by the MODE2, MODE1, and MODE0 pins. Selection MODE[2:0] Mode Description Sleep mode OUT and BUF outputs. ...

Page 20

For the opposite case: SIG+ = -0. 1. -1.4 V SIG- = -0. 1. +1.1 V SIG+ is -2.5 V relative to SIG- So the total swing for SIG+ relative to SIG- ...

Page 21

In DC differential output mode (MODE 5) the level-shifting buffer circuitry adds low-level 32 kHz switched-capacitor noise to the DC output. This noise is out of the measurement bandwidth for systems CS3301A / CS3302A amplifiers CS5371A / CS5372A modulators, and ...

Page 22

SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ VA- 6. DIGITAL INPUTS The CS4373A is designed to operate with the CS5376A digital filter. The digital filter gener- ates one-bit ∆Σ test bit stream data (TDATA), ...

Page 23

The timing accuracy of the input SYNC signal from measurement node to measurement node must be +/- 1 MCLK to maximize MSYNC analog sample synchronization accu- racy. The CS4373A ...

Page 24

SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ VA- 7. ANALOG OUTPUTS The CS4373A has multiple differential analog outputs. The best possible analog perfor- mance is achieved from the precision outputs (OUT±), but with only ...

Page 25

When enabled, attenuation is applied to both the OUT and BUF differential analog outputs. The OUT± pins connect directly into the inter- nal attenuator resistors and so attenuation ac- curacy is highly sensitive to load impedance on the OUT± pins. ...

Page 26

To VA+ Regulator 100 µF To VA- Regulator 100 µF 8. VOLTAGE REFERENCE The CS4373A requires a 2.500 V precision voltage reference to be supplied to the VREF pins. 8.1 VREF Power Supply To guarantee proper regulation headroom for the ...

Page 27

VREF Input Impedance The switched-capacitor input architecture of ± the VREF inputs results in an input imped- ance that depends on the internal capacitor size and the clock frequency. With in- ternal capacitor and a 2.048 ...

Page 28

To VA+ Regulator To VA- Regulator 100 uF 9. POWER SUPPLIES The CS4373A has a positive analog power supply pin (VA+), a negative analog power supply pin (VA-), a digital power supply pin (VD), and a ground pin (GND). For ...

Page 29

Power Supply Characteristics 9.4 SCR Latch-up The VA- pin is tied to the CS4373A CMOS substrate and must always be the most-nega- tive voltage applied to the device to ensure SCR latch-up does not occur. In general, ...

Page 30

TERMINOLOGY • Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated rms noise from DC to 430 Hz. The following formula is used to calculate SNR: SNR = 20log • Total ...

Page 31

PIN DESCRIPTION Positive Capacitor Output Negative Capacitor Output Positive Buffered Output Negative Buffered Output Positive High Precision Output Negative High Precision Output Positive Analog Power Supply Negative Analog Power Supply Negative Voltage Reference Positive Voltage Reference No Connect No ...

Page 32

Pin Name Pin # I/O ATT2, 22, I Attenuation Range. Selects the output attenuation range. 23, ATT1, 24 ATT0 Selection MODE2, 25, I Mode Selection. Determines the operational mode of the device. ...

Page 33

PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 A2 0.064 b 0.009 D 0.390 E 0.291 E1 0.197 e 0.022 L 0.025 ∝ 0° Notes: 1. “D” ...

Page 34

INFORMATION Model CS4373A-ISZ (lead free) 14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS4373A-ISZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 15.REVISION HISTORY Revision Date PP1 MAR 2003 Preliminary release for CS4373. PP2 SEP 2005 ...

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