DC-VIDEO-TVP5146N Altera, DC-VIDEO-TVP5146N Datasheet - Page 310
![VIDEO DAUGHTER CARD](/photos/9/6/90687/dc-video-tvp5146n_sml.jpg)
DC-VIDEO-TVP5146N
Manufacturer Part Number
DC-VIDEO-TVP5146N
Description
VIDEO DAUGHTER CARD
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.DC-VIDEO-TVP5146N.pdf
(58 pages)
Specifications of DC-VIDEO-TVP5146N
Main Purpose
Video, Daughter Card
Embedded
No
Utilized Ic / Part
Altera Dev Kits
Primary Attributes
Dual Composite Video Input - NTSC or PAL
Secondary Attributes
10-bit BT.656 Output, Compatible with Expansion Connector, Standard on Most Altera Development Kits
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1704
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- Download datasheet (4Mb)
1–310
Dedicated Clock Pin Timing
Table 1–142. EP3SL50 Column Pin Global Clock Timing Specifications
Table 1–143. EP3SL50 Row Pin Global Clock Timing Specifications
Table 1–144. EP3SL50 Column Pin Regional Clock Timing Specifications (Part 1 of 2)
Stratix III Device Handbook, Volume 2
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
Industrial
Industrial
Industrial
-0.034
-0.018
-0.018
1.732
1.650
0.048
1.689
1.689
1.736
1.736
Fast Model
Fast Model
Fast Model
Table 1–141
driven by the global clock, regional clock, periphery clock, and a PLL.
Table 1–141
Table 1–141. Clock Timing Parameters for Stratix III Devices
EP3SL50 Clock Timing Parameters
Table 1–142
devices.
Table 1–144
devices.
t
t
t
t
CIN
COUT
PLLCIN
PLLCOUT
Commercial
Commercial
Commercial
Symbol
-0.026
-0.026
1.843
1.752
0.116
0.025
1.669
1.669
1.737
1.737
to
lists the Stratix III clock timing parameters.
and
and
Table 1–201
Table 1–143
Table 1–145
-0.142 -0.216 -0.181
-0.284 -0.379 -0.362
2.527
2.385
2.371
2.371
-0.261
-0.261
1.1 V
1.1 V
2.436
2.436
V
V
1.1 V
V
Delay from the clock pad to the I/O input register
Delay from the clock pad to the I/O output register
Delay from the PLL inclk pad to the I/O input register
Delay from the PLL inclk pad to the I/O output register
C2
C2
CCL
CCL
C2
CCL
=
=
=
2.758
2.595
2.645
2.645
-0.312
-0.312
1.1 V
1.1 V
V
V
2.691
2.691
list clock pin timing for Stratix III devices when the clock is
1.1 V
V
C3
C3
CCL
CCL
C3
CCL
list the global clock timing parameters for EP3SL50
list the regional clock timing parameters for EP3SL50
=
=
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
3.099
2.918
3.004
3.004
1.1 V
1.1 V
-0.251
-0.251
V
V
3.056
3.056
1.1 V
V
C4
C4
CCL
CCL
C4
CCL
=
=
=
-0.136
-0.307
2.997
2.826
2.719
2.719
1.1 V
1.1 V
-0.230
-0.230
V
V
2.925
2.925
1.1 V
V
CCL
CCL
CCL
=
=
=
C4L
C4L
C4L
Parameter
-0.188
-0.347
3.227
3.068
3.136
3.136
0.9 V
0.9 V
V
V
-0.011
-0.011
3.433
3.433
0.9 V
V
CCL
CCL
CCL
=
=
=
-0.173
-0.343
2.811
2.641
2.645
2.645
1.1 V
1.1 V
V
V
-0.312
-0.312
2.691
2.691
1.1 V
V
I3
CCL
I3
CCL
I3
CCL
=
=
=
© July 2010 Altera Corporation
3.146
2.957
0.265
0.076
3.009
3.009
1.1 V
1.1 V
V
V
3.056
3.056
0.161
0.161
1.1 V
I4
CCL
I4
CCL
V
I4
CCL
=
=
=
-0.087 -0.230
-0.266 -0.389
3.055
2.876
2.719
2.719
1.1 V
1.1 V
V
V
-0.230
-0.230
2.925
2.925
1.1 V
CCL
CCL
V
CCL
=
=
=
I4L
I4L
I/O Timing
I4L
3.260
3.101
3.136
3.136
0.9 V
0.9 V
V
V
-0.011
-0.011
3.433
3.433
CCL
CCL
0.9 V
V
CCL
=
=
=
Units
Units
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
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