STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 23

• Manufacturer Part Number: STEVAL-PCC010V1
• Description: BOARD EVAL FOR ST802RT1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-PCC010V1

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST802RT1
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10360

ST802RT1A, ST802RT1B
Table 14.
4:0
Bit
15
14
13
12
11
10
9
8
7
6
5
10BASE-T full
Remote Fault
100BASE-T4
100BASE-TX
100BASE-TX
RESERVED
RESERVED
Asymmetric
Pause (full-
Pause (full-
10BASE-T
Next Page
full duplex
Bit name
Selector
duplex)
duplex)
duplex
RN04 [0d04, 0x04]: Auto-negotiation advertisement register
Next page: The ST802RT1x supports next page capability.
Reserved: Ignore output when read.
Remote fault: Writing a “1” to bit 13 of the advertisement register causes a remote fault
indicator to be sent to the link partner during auto-negotiation. Writing a “0” to this bit or
resetting the chip clears the remote fault transmission bit. This bit returns the value last
written to it, or else “0” if no write has been completed since the last chip reset.
Asymmetric pause: write '1' if asymmetric pause is supported by MAC when full-duplex link
is available. 1 = Advertise that the DTE (MAC) has implemented both the optional MAC
control sub layer and the pause function as specified in clause 31 and annex 31B of 802.3u.
0 = No MAC based full-duplex flow control.
Pause: The use of this bit is independent of the negotiated data rate, medium, or link
technology. The setting of this bit indicates the availability of additional DTE capability when
full-duplex operation is in use. This bit is used by one MAC to communicate symmetric
pause capability to its link partner, and has no effect on PHY operation.
Advertisement bits: Bits 9:5 of the advertisement register allow the user to customize the
ability information transmitted to the link partner. The default value for each bit reflects the
abilities of the ST802RT1x. By writing a “1” to any of the bits, the corresponding ability is
transmitted to the link partner. Writing a “0” to any bit causes the corresponding ability to be
1 -> Next page transfer supported
0 -> Next page transfer not supported
---
1 -> Advertises that this device has detected a remote fault
during auto-negotiation
0 -> No remote fault detected.
---
1 -> Asymmetric pause supported (MAC level)
0 -> No MAC based full-duplex flow control.
1 -> Symmetric pause supported (MAC level)
0 -> No MAC based full-duplex flow control.
0 -> 100BASE-T4 not supported
1 -> 100BASE-TX Full-duplex is supported by the local device
0 -> 100BASE-TX Full-duplex is not supported
1 -> 100BASE-TX is supported by the local device
0 -> 100BASE-TX is not supported
1 -> 10BASE-T Full-duplex is supported by the local device
0 -> 10BASE-T Full-duplex is not supported
1 -> 10BASE-T is supported by the local device
0 -> 10BASE-T is not supported
00001 -> IEEE802.3u
Doc ID 17049 Rev 1
Description
Registers and descriptors description
Default
00001b
Strap
Strap
Strap
Strap
0
0
0
0
0
1
0
type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
23/58
P
-
-
-
-
-
-
-
-
-
-
-