STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 17

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STEVAL-PCC010V1

Manufacturer Part Number
STEVAL-PCC010V1
Description
BOARD EVAL FOR ST802RT1
Manufacturer
STMicroelectronics

Specifications of STEVAL-PCC010V1

Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST802RT1
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
MII, RMII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10360

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STEVAL-PCC010V1
Manufacturer:
STMicroelectronics
Quantity:
3
ST802RT1A, ST802RT1B
6
6.1
Table 8.
Extended registers
Shadow registers
1Ch – 28d
1Bh – 27d
1Eh – 30d
10h – 16d
11h – 17d
12h – 18d
13h – 19d
14h – 20d
18h – 24d
19h – 25d
1Fh - 31d
1Bh - 27d
Address
00h – 0d
01h – 1d
02h – 2d
03h – 3d
04h – 4d
05h – 5d
06h – 6d
07h – 7d
08h – 8d
Registers and descriptors description
All of the management data control and status registers in the ST802RT1x's register set are
accessed via a Write or Read operation on the serial MDIO port. This access requires a
protocol described in the MII management interface section.
Register list
List of registers
RN1B
RN1C
RN1E
Index
RN00
RN01
RN02
RN03
RN04
RN05
RN06
RN07
RN08
RN10
RN11
RN12
RN13
RN14
RN18
RN19
RN1F
RS1B
Reg.
PHYID1
PHYID2
AMPHY
ANEGX
LDNPG
XRCNT
XCCNT
XDCNT
CNTRL
LPNPG
AUXCS
AUXSS
AUXM2
LDADV
XCNTL
BTEST
AUXS2
LPADV
STATS
XSTAT
TSTAT
Name
Default
0x05E1
0x0004
0x000A
0x000A
0x0000
0x7849
0x0203
0x8461
0x0000
0x2001
0x0000
0x1200
0x0000
0x0100
0x0140
0x0027
0x0000
0x0820
0x0000
0x0000
0x0000
value
Doc ID 17049 Rev 1
Control register
Status register
PHY identifier register Hi
PHY identifier register Lo
Auto-negotiation advertisement register
Auto-negotiation link partner ability register
Auto-negotiation expansion register
Auto-negotiation next page transmit register
Auto-negotiation link partner received next page register
RMII-TEST control register
Receiver configuration information and interrupt status register
Receiver event interrupts register
100Base-TX control register
Receiver mode control register
Auxiliary control register
Auxiliary status register
Auxiliary mode 2 register
10Base-T error and general status register
Auxiliary PHY register
Shadow Registers enable register
MISC/status/error/test shadow register
Registers and descriptors description
Register description
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