STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 22
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STEVAL-PCC010V1
Manufacturer Part Number
STEVAL-PCC010V1
Description
BOARD EVAL FOR ST802RT1
Manufacturer
STMicroelectronics
Datasheets
1.ST802RT1AFR.pdf
(58 pages)
2.STEVAL-PCC010V1.pdf
(37 pages)
3.STEVAL-PCC010V1.pdf
(9 pages)
Specifications of STEVAL-PCC010V1
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST802RT1
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
MII, RMII
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10360
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STEVAL-PCC010V1
Manufacturer:
STMicroelectronics
Quantity:
3
Registers and descriptors description
Table 12.
Table 13.
22/58
15:0
15:10
Bit
9:4
3:0
Bit
OUI MSBs
Bit name
REVISION
OUI LSBs
NUMBER
NUMBER
Bit name
MODEL
Reserved bits: Ignore ST802RT1x output when these bits are read.
Preamble suppression: This bit is a read-only bit and can be set by bit 1 of the RN14
register. When read as a logic “1”, the ST802RT1x is able to accept MII management
frames with or without the standard preamble pattern. When preamble suppression is
enabled (RN14[1]=1), only 2 preamble bits are required between successive management
commands, instead of the normal 32.
Auto-negotiation complete: Bit 5 of the status register returns a “1” if the auto-negotiation
process has been completed, and the contents of registers 4, 5, and 6 are valid.
Link status: The ST802RT1x returns a “1” on bit 2 of the status register when the link state
machine is in link pass, indicating that a valid link has been established. Otherwise, it
returns a “0”. When a link failure occurs after the link pass state has been entered, the link
status bit is latched at “0” and remains so until the bit is read. After the bit is read, it becomes
“1” if the link pass state has been entered again.
Jabber detect: 10BASE-T operation only. The ST802RT1x returns a “1” on bit 1 of the
status register if a jabber condition has been detected. After the bit is read, or if the chip is
reset, it reverts to “0”.
Extended register ability: Because the ST802RT1x supports extended register capability,
this read-only bit is always “1”. The ST802RT1x extended registers with their bit functions
are described in later sections of this document.
The PHY identifier registers #1 and #2 consist of a sum of the organizationally unique
identifier (OUI), the vendor's model number and the model revision number. ST's IEEE
assigned OUI is 0x0080E1.
RN02 [0d02, 0x02]: PHY identifier register Hi
RN03 [0d03, 0x03]: PHY identifier register Lo
Organizationally unique identifier (OUI), bits 3..18
OUI bits 1 and 2 are fixed to 0 by standard; ST OUI = 0080E1
Organizationally unique identifier (OUI), bits 19..24
Manufacturer’s model number
Allows identification of the revision of the device via software
reading of the register
Description
Description
Doc ID 17049 Rev 1
ST802RT1A, ST802RT1B
100001b
000110b
Default
Default
0001b
0203h
type
type
RW
RO
RW
RO
RO
RO
Type
Type
P
P
P
P