STEVAL-PCC010V1 STMicroelectronics, STEVAL-PCC010V1 Datasheet - Page 13

• Manufacturer Part Number: STEVAL-PCC010V1
• Description: BOARD EVAL FOR ST802RT1
• Manufacturer: STMicroelectronics

Specifications of STEVAL-PCC010V1

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ST802RT1
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: MII, RMII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10360

ST802RT1A, ST802RT1B
Table 4.
Data interface
MII control interface
Physical (twisted pair) interface
Pin n°
40
42
43
44
45
38
37
46
39
31
30
35
5
6
7
8
7
2
1
9
RX_CLK
TX_CLK
CRSDV
RXDV /
Pin functions of the ST802RT1x
TX_EN
MDINT
RXER
Name
RXD3
RXD2
RXD1
RXD0
TXD0
TXD1
TXD2
TXD3
SCLK
MDIO
MDC
CRS
COL
X1
I/O, PU
O, PD
O, PD
O, PD
Type
I, PD
OD
O
O
O
O
I
I
I
I
Transmit data. The media access controller (MAC) drives data to the
ST802RT1x using these inputs.
txd0 = MII/RMII tx data
txd1 = MII/RMII tx data
txd2/txd3 = MII tx data
RMII clock (50 Mhz)
MII transmit enable. The MAC asserts this signal when it drives valid data on
the txd inputs.
MII transmit clock. Normally the ST802RT1x drives tx_clk.
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps operation
Receive error. The ST802RT1x asserts this output when it receives invalid
symbols from the network.
Receive data. The ST802RT1x drives received data on these outputs.
rxd0 = MII/RMII rx data
rxd1 = MII/RMII rx data
rxd2/rxd3 = MII rx data
Receive data valid. (MII = RXDV, RMII = CRSDV). The ST802RT1x asserts
this signal when it drives valid data on rxd.
MII receive clock. This continuous clock provides reference for rxd, rx_dv, and
rx_er signals.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
MII collision detection. The ST802RT1x asserts this output when detecting a
collision. This output remains high for the duration of the collision. This signal is
asynchronous and inactive during full-duplex operation.
MII carrier sense. During half-duplex operation (RN00[8]=0), the ST802RT1x
asserts this output when either transmit or receive medium is non idle. During
full-duplex operation (RN00[8]=1), crs is asserted only when the receive
medium is non-idle.
Management data clock. Clock for the MDIO serial data channel. One MDC
transition is also required to complete a device reset.
Maximum frequency is 2.5 MHz.
Management data input/output. Bi-directional serial data channel for PHY
communication.
Management data interrupt.
Xtal in (25 Mhz). 25 MHz reference clock input. When an external 25 MHz
crystal is used, this pin must be connected to one of its terminals. If an external
25 MHz oscillator clock source is used, then this pin will be its input pin.
Doc ID 17049 Rev 1
Function
Pin description
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