C8051F700-TB Silicon Laboratories Inc, C8051F700-TB Datasheet - Page 42

BOARD PROTOTYPE WITH C8051F700

C8051F700-TB

Manufacturer Part Number
C8051F700-TB
Description
BOARD PROTOTYPE WITH C8051F700
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of C8051F700-TB

Accessory Type
Target Board
Processor To Be Evaluated
C8051F700
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1637
C8051F700
C8051F70x/71x
42
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 3x3 array of 1.20 mm square openings on 1.40 mm pitch should be used for the center ground pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
based on a Fabrication Allowance of 0.05 mm.
to be 60 µm minimum, all the way around the pad.
paste release.
Dimension
C1
C2
X1
X2
Y1
Y2
e
 
Table 6.2. QFN-48 PCB Land Pattern Dimensions
Figure 6.2. QFN-48 PCB Land Pattern
Rev. 1.0
6.80
6.80
0.20
4.00
0.75
4.00
Min
0.50 BSC
Max
6.90
6.90
0.30
4.10
0.85
4.10

Related parts for C8051F700-TB