C8051F700-TB Silicon Laboratories Inc, C8051F700-TB Datasheet - Page 146

• Manufacturer Part Number: C8051F700-TB
• Description: BOARD PROTOTYPE WITH C8051F700
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-TB

• Accessory Type: Target Board
• Processor To Be Evaluated: C8051F700
• Processor Series: C8051F7xx
• Interface Type: USB
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051F7xx
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1637; C8051F700

C8051F70x/71x
21.3. INT0 and INT1 External Interrupts
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “33.1. Timer 0 and Timer 1” on page 264) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 21.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “28.3. Priority Crossbar
Decoder” on page 185 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
146
IT0
1
1
0
0
IN0PL
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
INT0 Interrupt
Rev. 1.0
IT1
1
1
0
0
IN1PL
1
1
0
0
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
INT1 Interrupt