C8051F700-TB Silicon Laboratories Inc, C8051F700-TB Datasheet - Page 201

BOARD PROTOTYPE WITH C8051F700

C8051F700-TB

Manufacturer Part Number
C8051F700-TB
Description
BOARD PROTOTYPE WITH C8051F700
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of C8051F700-TB

Accessory Type
Target Board
Processor To Be Evaluated
C8051F700
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
7 V to 15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1637
C8051F700
SFR Definition 28.19. P2MDOUT: Port 2 Output Mode
SFR Address = 0xA6; SFR Page = F
SFR Definition 28.20. P2SKIP: Port 2 Skip
SFR Address = 0xD6; SFR Page = F
Name
Reset
Name
Reset
Bit
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
Bit
7:0
Type
Type
Bit
Bit
P2SKIP[3:0]
Name
Name
7
0
7
0
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
6
6
0
0
5
0
5
0
Rev. 1.0
P2MDOUT[7:0]
4
0
4
0
P2SKIP[7:0]
R/W
R/W
Function
Function
3
0
3
0
C8051F70x/71x
2
0
2
0
1
0
1
0
0
0
0
0
201

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