MT4LSDT864AY-13EG2 Micron Technology Inc, MT4LSDT864AY-13EG2 Datasheet - Page 7

• Manufacturer Part Number: MT4LSDT864AY-13EG2
• Description: MODULE SDRAM 64MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864AY-13EG2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 8Mx64
• Total Density: 64MByte
• Chip Density: 128Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 660mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Serial Presence-Detect Operation
Initialization
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
The Micron MT4LSDT464A, MT4LSDT864A(I), and MT4LSDT1664A(I) are high-speed
CMOS, dynamic random access, 32MB, 64MB, and 128MB memory modules organized
in a x64 configuration. These modules use SDRAM devices which are internally config-
ured as quad-bank DRAMs with a synchronous interface (all signals are registered on the
positive edge of the clock signals CK).
Read and write accesses to the SDRAM module are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank, A0–A11 for 32MB and 64MB; A0–A12 for 128MB select the device
row). The address bits registered coincident with the READ or WRITE command (A0–A7
for 32MB; A0–A8 for 64MB and 128MB) are used to select the starting device column
location for the burst access.
These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8
locations, or the full page with a burst terminate option. An auto precharge function
may be enabled to provide a self-timed row precharge that is initiated at the end of the
burst sequence. These modules use an internal pipelined architecture to achieve high-
speed operation. This architecture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed on every clock cycle to achieve
a high-speed, fully random access. Precharging one device bank while accessing one of
the other three device banks will hide the PRECHARGE cycles and provide seamless,
high-speed, random access operation.
These modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs,
outputs, and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more information regarding SDRAM operation, refer to
the 64Mb, 128Mb, or 256Mb SDRAM component data sheets.
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM’s SCL (clock) and SDA (data) signals. Write protect (WP) is tied to
ground on the module, permanently disabling hardware write protect.
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once power is
applied to V
DD
and V
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
DD
Q (simultaneously) and the clock is stable (stable clock is
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2002 Micron Technology, Inc. All rights reserved.