MT4LSDT864AY-13EG2 Micron Technology Inc, MT4LSDT864AY-13EG2 Datasheet - Page 12

• Manufacturer Part Number: MT4LSDT864AY-13EG2
• Description: MODULE SDRAM 64MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864AY-13EG2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 8Mx64
• Total Density: 64MByte
• Chip Density: 128Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 660mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5:
CAS Latency (CL)
Operating Mode
Write Burst Mode
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
CAS Latency Diagram
COMMAND
COMMAND
CL is the delay, in clock cycles, between the registration of a READ command and the
availability of the first piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 7 on page 13 indicates the operating
frequencies at which each CL setting can be used.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
CL = 2
NOP
NOP
T1
T1
t
t AC
LZ
CL = 3
12
T2
NOP
T2
NOP
t
t AC
D
LZ
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
Don’t Care
Undefined
T4
Mode Register Definition
©2002 Micron Technology, Inc. All rights reserved.