MT4LSDT864AY-13EG2 Micron Technology Inc, MT4LSDT864AY-13EG2 Datasheet - Page 14

• Manufacturer Part Number: MT4LSDT864AY-13EG2
• Description: MODULE SDRAM 64MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864AY-13EG2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 8Mx64
• Total Density: 64MByte
• Chip Density: 128Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 660mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 8:
PDF: 09005aef8078bc7c/Source: 09005aef8078bcd3
SD4C4_8_16X64AG.fm - Rev. D 1/07 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ
burst)
WRITE (select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table – Commands and DQMB Operation
Notes appear below; CKE is HIGH for all commands shown except SELF REFRESH
Notes:
This truth table provides a general reference of available commands. For a more detailed
description of commands and operations, refer to the 64Mb, 128Mb, or 256Mb SDRAM
component data sheet.
1. A0–A11 define the op-code written to the mode register, and for the 128MB module, A12
2. A0–A11 (32MB and 64MB) or A0–A12 (128MB) provide device row address, and BA0, BA1
3. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH
4. A10 LOW: BA0, BA1 determine the device bank being precharged. A10 HIGH: All device
5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care”
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
should be driven LOW.
determine which device bank is made active.
enables the auto precharge feature (nonpersistent) while A10 LOW disables the auto pre-
charge feature; BA0, BA1 determine which device bank is being read from or written to.
banks precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
32MB, 64MB, 128MB (x64, SR) 168-Pin SDRAM UDIMM
CS#
H
L
L
L
L
L
L
L
L
–
–
RAS# CAS# WE# DQMB Address
14
X
H
H
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
7
7
Bank/row
Bank/col
Bank/col
Op-code
Code
X
X
X
X
–
–
©2002 Micron Technology, Inc. All rights reserved.
High-Z
Active
Active
Valid
DQs
X
X
X
X
X
X
X
Commands
Notes
5, 6
1
3
3
4
1
7
7