IDT88K8483BRI IDT, Integrated Device Technology Inc, IDT88K8483BRI Datasheet - Page 71

• Manufacturer Part Number: IDT88K8483BRI
• Description: IC SPI-4 EXCHANGE 3PORT 672-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88K8483BRI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 88K8483BRI

Design Consideration
System Reset
Hardware Reset
Software Reset
to a hardware rest except that software reset does not change the N field in the
generators. After software reset the microprocessor should have delay of at least 2ms before accessing the device.
Power On Sequence
RCLK (SPI4A_RCLK, SPI4B_RCLK, SPI4M_RCLK), VDD (VDD33, VDDL25, VDDH25, VDDH15, VDDL12, VDDC12, VTT) and RESETB (RESETB).
Figure 38 Power-on-Reset Sequence p.71
recommends powering up the 3.3V (VDD33) power supply first, the 2.5V (VDDL25, VDDH25) power supply second, the 1.5V (VDDH15) power supply
third, the 1.2V (VDDC12, VDDL12) power supply fourth, and the 0.75V (VTT) power supply last. The power supplies can be also powered up in the
same time. There is no requirement for the minimum or maximum delay between the power-up of the power supplies. The power supplies should be
powered off in the reverse order. The power ramp should not be faster than 100us.
uration signals are stable, the RESETB signal should remain at a low level at least 10ms (symbol “T1”) to reset the internal logic. After the RESETB
pulse ends, the device starts generating the SPI-4 external output clocks and the MCLK internal clock.
IDT IDT88K8483
VDD33
VDDC12
RESETB
There are two methods for resetting the IDT88K8483: hardware reset and software reset. During reset the output clocks are not toggled.
The RESETB input requires an active low pulse to reset the internal logic.
The software reset is triggered by setting to 1 the RST field in
A correct power-on-reset sequence is crucial for the normal behavior of the device. The power-on-reset sequence includes the following signals:
When the power supplies are powered up, the RESETB signal should be at low level. During power-on-reset, after the VDD, RCLK and the config-
RCLK
.
.
.
illustrates the recommended implementation for the power-on-reset sequence for the device. IDT
Figure 38 Power-on-Reset Sequence
Global Software Reset Register (p.
71 of 162
T1
MCLK Divider Sticky Register (p.
T2
90). The response to a software reset is identical
T3
104), so it does not impact the clock
October 20, 2006