IDT88K8483BRI IDT, Integrated Device Technology Inc, IDT88K8483BRI Datasheet - Page 120
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IDT88K8483BRI
Manufacturer Part Number
IDT88K8483BRI
Description
IC SPI-4 EXCHANGE 3PORT 672-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT88K8483BRI.pdf
(162 pages)
Specifications of IDT88K8483BRI
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
88K8483BRI
- Current page: 120 of 162
- Download datasheet (3Mb)
SPI-4 Egress Status Clock Timing Register
Packet Fragment Processor (PFP) Registers
PFP Buffer Segment Assign Table
SCTC[0:3]
M
Reserved
THR_STARV
THR_HUNG
IDT IDT88K8483
There are 64 registers in this table, one for each LID.
Field
Field
Table 93
Table 94 PFP Buffer Segment Assign Table (Block Base=0x01000/0x1800, Register Offset=0x00-0x3F)
R/W
R/W
R
R/W
R/W
Read /
Read /
Write
Write
SPI-4 Egress Status Clock Timing Control (Block Base=0x0900, Register Offset=0x2E)
0:0-0:3
0:0-1:0
1:1-1:7
2:0-2:7
3:0-3:7
Bits
Bits
4
9
7
8
8
Length
Length
0
0
0
0
Reset
Reset
State
State
120 of 162
This register is used to manually align the phase of the SPI-4 egress status clock
to the status outputs by adding from 0.1 clock cycle to 0.9 clock cycles of delay
to the status clock output. Note that the clock delay value is not monotonically
related to the value encoded in the bit field [3:0].
The SCTC[3:0] field is valid only for LVDS status, not for LVTTL
status.
SCTC [3:0] Used for adding 0.1 unit intervals of output delay to the SPI-
4 egress status clock output.
[3:0]=0=No added delay
[3:0]=1=Add 0.1 clock cycle of delay t o the SPI-4 egress status clock
[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress status clock
[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress status clock
[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress status clock
[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress status clock
[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress status clock
[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress status clock
[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress status clock
[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress status clock
Maximum number of data buffer segments per LID of the available 508 segments in
the PFP.
Indicates the starving threshold. Status is set to starving if the number of free seg-
ments in the data buffer is more than or equal to the starving threshold
Indicates the hungry threshold. Status is set to hungry if the number of free seg-
ments in the data buffer is less than or equal to the starving thresholds but greater
than or equal to the hungry threshold.
Status is set to satisfied if the number of free segments in the data buffer is greater
than the hungry threshold.
Description
Description
October 20, 2006
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