IDT88K8483BRI IDT, Integrated Device Technology Inc, IDT88K8483BRI Datasheet
IDT88K8483BRI
Specifications of IDT88K8483BRI
Related parts for IDT88K8483BRI
IDT88K8483BRI Summary of contents
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Description The IDT88K8483 is a 3-port SPI-4 Exchange device. The IDT SPI-4 Exchange devices build on IDT’s proven SPI-4 implementation and packet fragment processor (PFP) design. The IDT88K8483 suits appli- cations with slow backpressure response and other advanced networking applications ...
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IDT IDT88K8483 Table Of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IDT IDT88K8483 List of Figures Figure 1. IDT88K8483 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IDT IDT88K8483 Figure 54. JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IDT IDT88K8483 List of Tables Table 1. IDT88K8483 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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IDT IDT88K8483 Table 54. SPI-4 Ingress LP to LID Mapping Table (Block Base=0x0000, Register Offset=0x00-0xff .105 Table 55. SPI-4 Ingress Calendar 0 ...
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IDT IDT88K8483 Table 108. PFP Ingress Status Monitor Register - 3 (Block Base=0x1700/0x1F00, Register Offset=0x07 .126 Table 109. PFP Ingress Status Monitor Register - 4 ...
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IDT IDT88K8483 Table 162. Version Number Register (Block Base=0x8B00, Register Offset=0x30 ...
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IDT IDT88K8483 Pin Assignment The following table shows the IDT88K8483 pins and their corresponding symbols. Function Pin ADR0 E1 ADR1 E2 ADR2 D2 ADR3 C4 ADR4 D3 ADR5 B4 BOND0 R6 BOND1 P6 CSB D5 DAT0 A5 DAT1 A4 DAT2 ...
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IDT IDT88K8483 Function Pin QDR_A3 N23 QDR_A4 N22 QDR_A5 P22 QDR_A6 P23 QDR_A7 P24 QDR_A8 P25 QDR_A9 P26 QDR_CQ N26 QDR_CQB N25 QDR_D0 D25 QDR_D1 H22 QDR_D10 K23 QDR_D11 K24 QDR_D12 K25 QDR_D13 M22 QDR_D14 M23 QDR_D15 K26 QDR_D16 H26 ...
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IDT IDT88K8483 Function Pin QDR_D34 W23 QDR_D35 W22 QDR_D4 F24 QDR_D5 H24 QDR_D6 F25 QDR_D7 H25 QDR_D8 D26 QDR_D9 K22 QDR_IMP AD25 QDR_K L26 QDR_KB L25 QDR_Q0 C25 QDR_Q1 G22 QDR_Q10 J23 QDR_Q11 J24 QDR_Q12 J25 QDR_Q13 L22 QDR_Q14 L23 ...
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IDT IDT88K8483 Function Pin QDR_Q32 Y23 QDR_Q33 Y22 QDR_Q34 V23 QDR_Q35 V22 QDR_Q4 E24 QDR_Q5 G24 QDR_Q6 E25 QDR_Q7 G25 QDR_Q8 C26 QDR_Q9 J22 QDR_RB K21 QDR_VREF AD26 QDR_WB L21 RDB C5 RESETB AF4 SPI4A_BIAS A24 SPI4A_CLK_SEL F21 SPI4A_ECTL_N D15 ...
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IDT IDT88K8483 Function Pin SPI4A_ED[3]_N C17 SPI4A_ED[3]_P C16 SPI4A_ED[4]_N B17 SPI4A_ED[4]_P B16 SPI4A_ED[5]_N A17 SPI4A_ED[5]_P A16 SPI4A_ED[6]_N E19 SPI4A_ED[6]_P E18 SPI4A_ED[7]_N D19 SPI4A_ED[7]_P D18 SPI4A_ED[8]_N C19 SPI4A_ED[8]_P C18 SPI4A_ED[9]_N B19 SPI4A_ED[9]_P B18 SPI4A_EDCLK_N A21 SPI4A_EDCLK_P A20 SPI4A_ESCLK_N A7 SPI4A_ESCLK_P A6 ...
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IDT IDT88K8483 Function Pin SPI4A_ID[13]_N A13 SPI4A_ID[13]_P A12 SPI4A_ID[14]_N C15 SPI4A_ID[14]_P C14 SPI4A_ID[15]_N B15 SPI4A_ID[15]_P B14 SPI4A_ID[2]_N B9 SPI4A_ID[2]_P B8 SPI4A_ID[3]_N A9 SPI4A_ID[3]_P A8 SPI4A_ID[4]_N E11 SPI4A_ID[4]_P E10 SPI4A_ID[5]_N D11 SPI4A_ID[5]_P D10 SPI4A_ID[6]_N C11 SPI4A_ID[6]_P C10 SPI4A_ID[7]_N B11 SPI4A_ID[7]_P B10 ...
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IDT IDT88K8483 Function Pin SPI4B_CLK_SEL AA21 SPI4B_ECTL_N AC15 SPI4B_ECTL_P AC14 SPI4B_ED[0]_N AB15 SPI4B_ED[0]_P AB14 SPI4B_ED[1]_N AB17 SPI4B_ED[1]_P AB16 SPI4B_ED[10]_N AF19 SPI4B_ED[10_P AF18 SPI4B_ED[11]_N AB21 SPI4B_ED[11]_P AB20 SPI4B_ED[12]_N AC21 SPI4B_ED[12]_P AC20 SPI4B_ED[13]_N AC22 SPI4B_ED[13]_P AB22 SPI4B_ED[14]_N AD21 SPI4B_ED[14]_P AD20 SPI4B_ED[15]_N AE21 ...
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IDT IDT88K8483 Function Pin SPI4B_ESCLK_N AF7 SPI4B_ESCLK_P AF6 SPI4B_ESCLK_T AC6 SPI4B_ESTA[0]_N AD7 SPI4B_ESTA[0]_P AD6 SPI4B_ESTA[1]_N AE7 SPI4B_ESTA[1]_P AE6 SPI4B_ESTA_T0 AB7 SPI4B_ESTA_T1 AC7 SPI4B_ICTL_N AB9 SPI4B_ICTL_P AB8 SPI4B_ID[0]_N AC9 SPI4B_ID[0]_P AC8 SPI4B_ID[1]_N AD9 SPI4B_ID[1]_P AD8 SPI4B_ID[10]_N AC13 SPI4B_ID[10]_P AC12 SPI4B_ID[11]_N AD13 ...
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IDT IDT88K8483 Function Pin SPI4B_ID[7]_N AE11 SPI4B_ID[7]_P AE10 SPI4B_ID[8]_N AF11 SPI4B_ID[8]_P AF10 SPI4B_ID[9]_N AB13 SPI4B_ID[9]_P AB12 SPI4B_IDCLK_N AF15 SPI4B_IDCLK_P AF14 SPI4B_ISCLK_N AF23 SPI4B_ISCLK_P AF22 SPI4B_ISCLK_T AD24 SPI4B_ISTA[0]_N AD23 SPI4B_ISTA[0]_P AD22 SPI4B_ISTA[1]_N AE23 SPI4B_ISTA[1]_P AE22 SPI4B_ISTA_T0 AC23 SPI4B_ISTA_T1 AC24 SPI4B_LVDSTA Y21 ...
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IDT IDT88K8483 Function Pin SPI4M_ED[14]_P Y3 SPI4M_ED[15]_N AA2 SPI4M_ED[15]_P Y2 SPI4M_ED[2]_N U4 SPI4M_ED[2]_P T4 SPI4M_ED[3]_N U3 SPI4M_ED[3]_P T3 SPI4M_ED[4]_N U2 SPI4M_ED[4]_P T2 SPI4M_ED[5]_N U1 SPI4M_ED[5]_P T1 SPI4M_ED[6]_N W5 SPI4M_ED[6]_P V5 SPI4M_ED[7]_N W4 SPI4M_ED[7]_P V4 SPI4M_ED[8]_N W3 SPI4M_ED[8]_P V3 SPI4M_ED[9]_N W2 ...
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IDT IDT88K8483 Function Pin SPI4M_ID[10]_P M4 SPI4M_ID[11]_N N3 SPI4M_ID[11]_P M3 SPI4M_ID[12]_N N2 SPI4M_ID[12]_P M2 SPI4M_ID[13]_N N1 SPI4M_ID[13]_P M1 SPI4M_ID[14]_N R3 SPI4M_ID[14]_P P3 SPI4M_ID[15]_N R2 SPI4M_ID[15]_P P2 SPI4M_ID[2]_N J2 SPI4M_ID[2]_P H2 SPI4M_ID[3]_N J1 SPI4M_ID[3]_P H1 SPI4M_ID[4]_N L5 SPI4M_ID[4]_P K5 SPI4M_ID[5]_N L4 ...
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IDT IDT88K8483 Function Pin SPI4M_ISTA_T1 AD4 SPI4M_LVDSTA AF5 SPI4M_RCLK AF3 SPI4M_VREF AD2 SPIEN E3 TCK M6 TDI W21 TDO N6 TESTSE J21 TIMEBASE AE4 TMS H21 TRSTB V21 WRB B5 VDDA25 AA17 VDDA25 AA10 VDDA25 F17 VDDA25 F10 VDDA25 G17 ...
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IDT IDT88K8483 Function Pin VDDC12 J16 VDDC12 J15 VDDC12 J14 VDDC12 J13 VDDC12 J12 VDDC12 J11 VDDC12 J10 VDDC12 J9 VDDC12 J19 VDDC12 J18 VDDC12 K10 VDDC12 K9 VDDC12 K19 VDDC12 K18 VDDC12 L10 VDDC12 L9 VDDC12 L19 VDDC12 L18 ...
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IDT IDT88K8483 Function Pin VDDC12 T18 VDDC12 U10 VDDC12 U9 VDDC12 U19 VDDC12 U18 VDDC12 V17 VDDC12 V16 VDDC12 V15 VDDC12 V14 VDDC12 V13 VDDC12 V12 VDDC12 V11 VDDC12 V10 VDDC12 V9 VDDC12 V19 VDDC12 V18 VDDC12 W17 VDDC12 W16 ...
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IDT IDT88K8483 Function Pin VDDL12 AA13 VDDL12 AA12 VDDL12 F13 VDDL12 F12 VDDL12 G13 VDDL12 G12 VDDL12 M8 VDDL12 M7 VDDL12 N8 VDDL12 N7 VDDL12 Y13 VDDL12 Y12 VDDL25 AA14 VDDL25 AA9 VDDL25 AA8 VDDL25 AA18 VDDL25 F14 VDDL25 F9 ...
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IDT IDT88K8483 Function Pin VDDT33 A2 VDDT33 AF25 VDDT33 AF2 VSS AA7 VSS AA6 VSS AB24 VSS AE25 VSS AE2 VSS B25 VSS B2 VSS E6 VSS E5 VSS F7 VSS F6 VSS F5 VSS G7 VSS G6 VSS H6 ...
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IDT IDT88K8483 Function Pin VSS M14 VSS M11 VSS N17 VSS N16 VSS N12 VSS N11 VSS P17 VSS P16 VSS P11 VSS R17 VSS R16 VSS R13 VSS R11 VSS T17 VSS T16 VSS T15 VSS T14 VSS T13 ...
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IDT IDT88K8483 Function Pin VSS F11 VSS G16 VSS G11 VSS K8 VSS K7 VSS T8 VSS T7 VSS Y16 VSS Y11 VSS K20 VSS L20 VSS P20 VSS AA20 VSS AA19 VSS F20 VSS F19 VSS AA15 VSS F15 ...
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IDT IDT88K8483 Function Pin VSS R15 VSS N14 VSS P13 VTT075 G20 VTT075 H20 VTT075 J20 VTT075 R20 VTT075 T20 VTT075 U20 A26 1 NP AF1 1 NP AF26 Table 1 IDT88K8483 Pinout (Part 19 ...
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IDT IDT88K8483 Pin Description Table The following table lists the functions of the pins provided on the IDT88K8483. Some of the functions listed are multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. ...
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IDT IDT88K8483 1 Symbol I/O Type SPI4A_ID[15:0]_P I LVDS SPI4B_ID[15:0]_P SPI4M_ID[15:0]_P SPI4A_ID[15:0]_N SPI4B_ID[15:0]_N SPI4M_ID[15:0]_N SPI4A_IDCLK_P I LVDS SPI4B_IDCLK_P SPI4M_IDCLK_P SPI4A_IDCLK_N SPI4B_IDCLK_N SPI4M_IDCLK_N SPI4A_ICTL_P I LVDS SPI4B_ICTL_P SPI4M_ICTL_P SPI4A_ICTL_N SPI4B_ICTL_N SPI4M_ICTL_N SPI4A_ISTA[1:0]_P O LVDS SPI4B_ISTA[1:0]_P SPI4M_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4B_ISTA[1:0]_N SPI4M_ISTA[1:0]_N SPI4A_ISCLK_P O ...
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IDT IDT88K8483 1 Symbol I/O Type QDR_D[35:0]/ O HSTL G_ECTL[3:0], G_EDAT[31:0] QDR_Q[35:0]/ I HSTL G_ICTL[3:0], G_IDAT[31:0] QDR_RB O HSTL QDR_WB O HSTL QDR_K / G_ECLKP O HSTL QDR_KB / G_ECLKN O HSTL QDR_CQ / G_ICLKP I HSTL QDR_CQB / G_ICLKN ...
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IDT IDT88K8483 1 Symbol I/O Type WRB/SDI I CMOS Pull-up Schmitt Trigger RDB / SCLK I CMOS Pull-up Schmitt Trigger CSB I CMOS Pull-up Schmitt Trigger INTB O CMOS Open Drain SPIEN I CMOS Pull-up MPM I CMOS Pull-up JTAG ...
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IDT IDT88K8483 1 Symbol I/O Type SPI4A_CLK_SEL I CMOS SPI4B_CLK_SEL Pull-up SPI4M_CLK_SEL Power Supply and Ground VDDC12 PWR VDDL12 PWR VDDH15 PWR VDDL25 PWR VDDH25 PWR VDDT33 PWR VDDA25 PWR VTT075 I/O VSS PWR BOND[1: table 2 ...
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IDT IDT88K8483 Functional Description The IDT88K8483 device is a three port SPI exchange device intended for use in Ethernet transport, SONET/SDH line cards, security firewalls, and multi-service switches. The SPI-4 interface is defined by the Optical Internetworking Forum. The device ...
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IDT IDT88K8483 QDR-II External Memory Structure The device can be connected to 18M bits QDR-II (2M usable data bytes) SRAM which can store segments of 256 bytes as shown in Figure 5 QDR-II SRAM Structure Example LIDs, ...
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IDT IDT88K8483 SPI-4 Ingress Port Buffer Structure Each SPI-4 physical port in the ingress direction has 32 port buffers of 128 bytes as shown in Figure 7 SPI-4 Ingress Port Buffer Structure p.35. The buffers can be concatenated so that ...
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IDT IDT88K8483 Data Path Detailed Description There are several data paths in the device as shown in the figures below. There are four PFPs in the device: PFP module A Tributary to Main (PFP-A-MT), PFP module A Main to Tributary ...
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IDT IDT88K8483 SPI-4 Egress SPI-4 Ingress Port Buffers SPI-4A Interface SPI-4 Egress SPI-4 Egress Port Buffers Tributary SPI-4s SPI-4 Egress SPI-4 Ingress SPI-4B Interface Port Buffers SPI-4 Egress SPI-4 Egress Port Buffers PFP loop data path is sending data from ...
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IDT IDT88K8483 SPI-4 Egress SPI-4 Ingress Port Buffer SPI-4A Interface SPI-4 Egress SPI-4 Egress Port Buffer Tributary SPI-4s SPI-4 Egress SPI-4 Ingress SPI-4B Interface Port Buffer SPI-4 Egress SPI-4 Egress Port Buffer Figure 12 Microprocessor, Auxiliary and Internal Traffic Detector/Generator ...
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IDT IDT88K8483 External Interfaces The external interfaces provided on the IDT88K8483 device are three SPI-4 interfaces, SPI-4A, SPI-4B and SPI-4M, an interface to either a FPGA or a QDR-II bus, a pin-selectable serial or parallel microprocessor interface, a JTAG interface, ...
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IDT IDT88K8483 Serial microprocessor interface: – Compliance to Motorola Serial Peripheral Interface (SPI) specification – Byte access – Direct accessed space used for quick interrupt processing – Expanded indirect access space used for provisioning – Read operations to a reserved ...
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IDT IDT88K8483 SPI-4 Interface Overview SPI-4.2 as originally defined is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device (network processor), for aggregate bandwidths of OC-192 ATM and Packet over SONET/SDH ...
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IDT IDT88K8483 SPI4A_ED[15:0]_P SPI4A_ED[15:0]_N SPI4A_EDCLK_P SPI4A_EDCLK_N SPI4A_ECTL_P SPI4A_ECTL_N SPI4A_ESTA[1:0]_P SPI4A_ESTA[1:0]_N SPI4A_ESCLK_P SPI4A_ESCLK_N SPI4A_ID[15:0]_P SPI4A_ID[15:0]_N SPI4A_IDCLK_P SPI4A_IDCLK_N SPI4A_ICTL_P SPI4A_ICTL_N SPI4A_ISTA[1:0]_P SPI4A_ISTA[1:0]_N SPI4A_ISCLK_P SPI4A_ISCLK_N SPI4A_LVDSSTA SPI4A_VREF SPI4A_BIAS IDT88K8483 SPI-4 Ingress Data Channel The SPI-4 ingress data channel is independent from the status ...
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IDT IDT88K8483 Bit alignment Skew control Bit alignment The bit alignment block is responsible for data and clock alignment. The bit alignment allows the clock to be used for correct data sampling and eliminate bit errors by providing adequate set-up ...
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IDT IDT88K8483 OUT_OF_SYNCH IN_SYNCH The bus word may be payload data word, payload control word, idle control word or training word classified by the CTL input signal and the content of the control field. The DIP fields of ...
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IDT IDT88K8483 If the I_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after the last ‘11’ framing pattern. If I_CSW_EN is set to 1, and I_DIP_CSW is set to 1, then the ...
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IDT IDT88K8483 Skew control Bit De-skew aligne Tx Machine Control words are inserted only between the transfers. Once a transfer has begun, the data words are sent uninterrupted until a whole transfer is complete. The interval between the end of ...
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IDT IDT88K8483 Egress associated status channel Bit alignment The alignment selection is programed by AUTO_ALIGN flag in the The device is responsible for edge transition histogram for each lane. The data is sampled by 10-phased shifted clock during each clock ...
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IDT IDT88K8483 If the E_CSW_EN field is cleared to 0, then the DIP-2 is computed over all preceding status indications after last ‘11’ framing pattern. If E_CSW_EN field is set to 1, and E_DIP_CSW field is set to 1, then ...
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IDT IDT88K8483 physical port SPI-4 logical port SPI-4 SPI 4 A SPI-4 SPI 4 B OBC insert extract The OBC insert and extract paths are provided on both directions of the packet fragment processor A. They are intended for low ...
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IDT IDT88K8483 t+258 t+1 t OBC insert The first byte indicates the SOP or EOP and also whether the packet is error tagged or not by writing into the ED bit. The second byte is the lid information, which tells ...
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IDT IDT88K8483 OBC extract The OBC extract process also works in the same way. The OBC extract FIFO can hold up to 256 bytes of data. The registers used in this process are PFP T-M extract control register (Register Offset=0x2) ...
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IDT IDT88K8483 Packet Fragment Processor (PFP) Overview SPI-4 SPI-4 Ingress Ingress Interface Port Buffer PFP The Packet Segment Pool (PFP internal block which is used for queuing and scheduling. There are four PFPs in the device - one ...
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IDT IDT88K8483 The egress also has the flexibility to be programmed for burst or non-burst mode and status or credit mode transfer control. When BURST_EN field in the PFP Flow Control Register (p. 125) the data buffer to the egress ...
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IDT IDT88K8483 PFP Ingress Flow Control for over booking mode There are 4 main parameters for configuring the PFP ingress flow control for over booking mode: - Maximum number of segments per LID is configured in M field in the ...
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IDT IDT88K8483 QDR-II Interface Overview The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is configured by the MEM field in the Auxiliary Interface Configuration Register (p. is enabled. ...
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IDT IDT88K8483 QDR-II Flow Control The IDT88K8483 gets the QDR-II FIFO status information from the QDR-II interface, and the PFP LID status information from the PFP logic. The IDT88K8483 can be configured to one of two different flow control modes ...
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IDT IDT88K8483 SPI-4 Ingress Ingress data Framer Interface status Interleaved Channels Flow Control Mode 2 - Buffering In the buffering option the IDT88K8483 gets the data in interleaved mode or in packet mode and it sends the data in packet ...
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IDT IDT88K8483 An application example for flow control mode 2 is described in pressure. SPI-4 Ingress Ingress data Framer Interface status Interleaved Channels Impedance Matching Control The auxiliary interface egress side has impedance matching control. It has on chip test ...
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IDT IDT88K8483 Generic Interface Overview The auxiliary interface has two modes: QDR-II interface mode and generic interface mode. The auxiliary interface mode (QDR-II or generic) is configured by the MEM field in the Auxiliary Interface Configuration Register (p. is enabled. ...
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IDT IDT88K8483 The LID field in the Transfer Format for Normal Data includes the LID number (LID0,LID2,LID3,...). The control field is encoded to indicate the type of data word as described in Table 4. ctrl[1], ctrl[0] 00000000 00000001 00000010 00000011 ...
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IDT IDT88K8483 Interface Operation The egress channel generates the transfer format and the local status information. The ingress channel detects the transfer format and status information from the adjacent device. Each word of the ingress interface is classified by decoding ...
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IDT IDT88K8483 Microprocessor Interface Overview The microprocessor interface can be in serial mode or in parallel mode. When the external signal SPIEN is cleared to 0, the interface is in parallel mode, and when SPIEN signal is set to 1, ...
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IDT IDT88K8483 Start ReadReg 0x16 ( EP_READY Result 1 1 ReadReg 0x14 ( IFIFO_STATUS Result 0 WriteReg 0x10 ( DATA Example for download sequence An example pseudo code of how the download sequence is implemented is shown below DOWNLOAD { ...
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IDT IDT88K8483 } // End of Download Interrupt The device captures events in the Register (p. 98) are cleared by writing 1 to the appropriate field. The device has two interrupt levels: a primary level and a secondary level. The ...
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IDT IDT88K8483 PMON PMON Events There are few event types: Field associated non-critical event, Field associated critical event, Non field associated events. The events are described in the tables below. When a Field associated non-critical event is captured, the LID ...
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IDT IDT88K8483 Event Name Tributary SPI4 ingress locker unavailable Main SPI4 ingress locker unavailable Tributary ingress data clock loss Tributary egress status clock loss Main ingress data clock loss Main egress status clock loss Tributary SPI4 DIP-2 Tributary SPI4 DIP-4 ...
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IDT IDT88K8483 OBC Insert Loop Ingress 1 SPI4 A locker Ingress 2 SPI4 A locker Loop AUX insert OBC extract Loop 21 Egress SPI4 A locker 22 Egress SPI4 B locker Loop AUX extract ...
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IDT IDT88K8483 Time base A single PMON time base is provided for the device. The time base can be generated internally or externally according to the INTERNAL field in PMON 1ms Timer Register (p. 145). The internal time base can ...
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IDT IDT88K8483 Tim ebase trigger TIM EBASE interrupt Clock IDT88K8483 has three programmable clock generators (main, tributary A and tributary B). One clock generator (main) is type M and two clock generators (tributary A and tributary B) are type T. ...
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IDT IDT88K8483 Clock Generator Type M Clock generator type M generates the internal clock MCLK and the external SPI-4 main interface clocks (EDCLK, ISCLK, ISCLK_T) as shown in Figure 36 Clock Generator Type M generator source is the external signal ...
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IDT IDT88K8483 Design Consideration System Reset There are two methods for resetting the IDT88K8483: hardware reset and software reset. During reset the output clocks are not toggled. Hardware Reset The RESETB input requires an active low pulse to reset the ...
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IDT IDT88K8483 After the RESETB pulse ends, a delay of 2ms should be added (symbols “T2” and “T3”) before accessing the device for initialization and configu- ration. This allows the internal logic to be stable. During T2 (at least 1ms ...
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IDT IDT88K8483 The internal JTAG logic of each device powers unknown state necessary at power-on to reset it to the Test-Logic-Reset state so that the chip operates properly. This can be done in one ...
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IDT IDT88K8483 Ensure that the buffer has sufficient drive capability to supply all loads. When using a buffer to drive any of the JTAG TAP pins, it may be necessary to include an external resistor to ensure the pin is ...
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IDT IDT88K8483 6. Connect the , V V SPI4A_VREF SPI4B_VREF SPI4x_VREF Filter Circuit p.75. 7. Generate the signals from the V /V QDR_VREF G_VREF 12V 470uF VIN 3.9K TRIM RMT_ON_OFF power_on signal from CPLD SIL06C-12SADJ-V (ARTESYN) 12V 470uF 3.9K power_on ...
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IDT IDT88K8483 Configuration Sequence Before writing the configuration flow, design and determine the device configuration including: – Specific application – Data path – Mapping relation between link and logic port – Working mode of each link The device configuration flow ...
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IDT IDT88K8483 Registers Register Organization: There are two types of register in the IDT88K8483: ◆ Direct Registers: Direct registers are used for high-priority registers such as interrupts and for access to the indirect registers. Direct registers can be accessed more ...
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IDT IDT88K8483 Direct Register Address (HEX) 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 The Indirect Register Accessing scheme: Address Name Segment Base 3 Module Base 2 Block Base 2 Register Offset 1 3 Byte Indirect register Address = 3 ...
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IDT IDT88K8483 Indirect Read and Write Operation: ◆ Indirect Write Access Operation – The OBC reads the BUSY flag in the Microprocessor Indirect Access Control Register (p. 93). It proceeds only when the flag is cleared. – The indirect WRITE ...
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IDT IDT88K8483 Register Map Direct Registers Map Register Offset ...
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IDT IDT88K8483 Register Offset Indirect Registers Map ◆ Indirect Register Addressing = Segment Base Address + Module Base Address + Block Base Address + Register_Offset Segment Base Address There are ...
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IDT IDT88K8483 Block Base Address and Register Offset There are block bases defined for module registers ( ) and for common ( ciated PMON, insert/extract Indirect Registers Map Module Block Base Base Name Address Address M:0x8000 CLK_GEN 0x0a00 M:0x8000 CLK_GEN ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 M:0x8000 A:0x0000 INGRESS_REG 0x0300 B:0x2000 ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG, 0x0800 B:0x2000 M:0x8000 A:0x0000 EGRESS_REG 0x0800 B:0x2000 ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 A:0x0000 SPI_TIMING 0x0900 B:0x2000 M:0x8000 BUFFER_ TM - 0x1000 A (TM) ASSIGN B (TM 0x1800 A (MT) ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address PACKET_ TM - 0x1600 A (TM) MODE B (TM 0x1E00 A (MT) B (MT) PFP TM Control Register group - 0x1700 PFP MT Control Register group - ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address TM_PFP_REG TM - 0x1700 A (TM) B (TM) MT_PFP_REG MT - 0x1F00 A (MT) B (MT) B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: 0x2000 AUXILIARY 0x0A00 B: ...
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IDT IDT88K8483 Module Block Block Base Base Base Name Address Address A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: 0x2000 A: 0x0000 PMON_EVENT 0x0F00 B: ...
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IDT IDT88K8483 Direct Registers Description Note: (1) All direct registers are 8 bits wide. (2) Unused bits are reserved bits. (3) A READ to unused/reserved bits returns 0 while a WRITE is ignored. Miscellaneous Registers Global Software Reset Register Read ...
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IDT IDT88K8483 Microprocessor Mailbox Input FIFO Status Register Read / Field Bits Write IFIFO_STATUS R 0:0 Table 22 Microprocessor Mailbox Input FIFO Status Register Microprocessor Mailbox Output FIFO Data Register Read / Field Bits Write Data R/W 0:0 - 0:7 ...
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IDT IDT88K8483 Microprocessor Mailbox Output FIFO Length Register Read / Field Bits Write Length R/W 0:0 - 0:5 Table 24 Microprocessor Mailbox Output FIFO Length Register Microprocessor Mailbox Output FIFO Status Register Read / Field Bits Write OFIFO_STATUS R 0:0 ...
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IDT IDT88K8483 External Microprocessor Registers Microprocessor Indirect Access Control Register Read / Field Bits Write ERROR R 0:0 - 0:5 RWN R/W 0:6 BUSY R 0:7 Table 27 Microprocessor Indirect Access Control Register Error Code ...
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IDT IDT88K8483 Microprocessor Indirect Access Data Register - 2 Read / Field Bits Write DATA[8:15] R/W 0:0 - 0:7 Table 30 Microprocessor Indirect Access Data Register - 2 Microprocessor Indirect Access Data Register - 3 Read / Field Bits Write ...
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IDT IDT88K8483 Microprocessor Indirect Access Data Register - 4 Read / Field Bits Write DATA[24:31] R/W 0:0 - 0:7 Table 32 Microprocessor Indirect Access Data Register - 4 Microprocessor Indirect Access Address Register - 1 Read / Field Bits Write ...
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IDT IDT88K8483 PFP T-M insert control register for module A Read/ Field Bits Write DATA_AVAILABLE R/W 0:0 Note: The DATA_AVAILABLE flag will self clear if FIFO is emptied by PFP. This event will be forwarded to interrupt module. Reset Length ...
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IDT IDT88K8483 PFP T-M insert data register for module A Read/ Field Write DATA W PFP T-M extract control register for module A Read/ Field Write DATA_AVAILABLE R/W 0:0 Note: After data is extracted from the FIFO, a transfer extract ...
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IDT IDT88K8483 PFP M-T extract control register for module A Read/ Field Write DATA_AVAILABLE R/W 0:0 Note: After data is extracted from the FIFO, a transfer extract event will be forwarded to the interrupt module. PFP M-T extract data register ...
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IDT IDT88K8483 Primary Interrupt Enable Register Read / Field Bits Write MODULE_A_EN R/W 0:0 MODULE_B_EN R/W 0:1 COMMON_EN R/W 0:2 Table 45 Primary Interrupt Enable Register Note: Please refer to Interrupt Scheme (p. 64) Reset Length State 1 0 This ...
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IDT IDT88K8483 Secondary Interrupt Module A Indication Register Read / Field Bits Write SPI-MT EXTRACT R/W 0:0 SPI-TM EXTRACT R/W 0:1 SPI-TM INSERT R/W 0:2 SPI-MTINSERT R/W 0:3 PMON R 0:4 Table 46 Secondary Module Indication Register Secondary Interrupt Module ...
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IDT IDT88K8483 Secondary Interrupt Module B Indication Register Read / Field Write Reserved PMON R Table 48 Secondary interrupt module B Indication register(Register Offset=0xC) Secondary Interrupt Module B Enable Register Read / Field Bits Write Reserved 0:0 - 0:3 PMON_EN ...
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IDT IDT88K8483 Secondary Interrupt COMMON Indication Register Read / Field Bits Write TIMEBASE R/W 0:0 INDIRECT_ACC R/W 0:1 I_FIFO_READY R/W 0:2 I_FIFO_OFLOW R/W 0:3 O_FIFO_MSG R/W 0:4 SOC R/W 0:5 10ms R/W 0:6 Table 50 Interrupt secondary COMMON indication register ...
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IDT IDT88K8483 Secondary Interrupt COMMON Enable Register Read / Field Bits Write TIMEBASE_EN R/W 0:0 INDIRECT_ACC_EN R/W 0:1 I_FIFO_READY_EN R/W 0:2 I_FIFO_OFLOW_EN R/W 0:3 O_FIFO_MSG_EN R/W 0:4 SOC_EN R/W 0:5 10ms_EN R/W 0:6 Note: Writing any field ...
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IDT IDT88K8483 Indirect Registers Description Note: (1) All indirect registers are 32 bits wide. (2) Treat unused bits as reserved bits. (3) A READ to unused/reserved bits returns 0 while a WRITE is ignored. Clock Registers MCLK Divider Sticky Register ...
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IDT IDT88K8483 SPI-4 Registers SPI-4 Ingress LP to LID Mapping Table Read / Field Bits Write N R/W 0:0 - 0:5 P R/W 0:6 Reserved ENABLE R/W 1:0 Table 54 SPI-4 Ingress LP to LID Mapping Table ...
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IDT IDT88K8483 SPI-4 Interface Enable Register Read / Field Bits Write SPI4_EN R/W 0:0 SPI4_PDN R/W 0:1 Note: (1) The SPI4 interface has to be configured before enabling the interface SPI-4 Interface Enable Register (Block Base= 0x0300, Register Offset=0x00) Table ...
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IDT IDT88K8483 SPI-4 Ingress Training Parameter Register Read / Field Bits Write FIFO_MAX_T R/W 0:0-2:7 ALPHA_FIFO R/W 3:0-3:7 Note: The purpose of the FIFO status path training sequence is for the deskew of bit arrival times on the FIFO status ...
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IDT IDT88K8483 SPI-4 Ingress Calendar 1 Configuration Register Read / Field Bits Write I_CAL_M R/W 0:0-0:7 I_CAL_LEN R/W 1:0-1:6 Note the I_CSW_EN bit in SPI4 Ingress Calendar Switch Control Register (p. 109) calendar sequence is repeated before a ...
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IDT IDT88K8483 SPI-4 Ingress Diagnostics Register Read / Field Bits Write I_FORCE_TRAIN R/W 0:0 I_ERR_INS R/W 0:1 I_DIP_NUM R/W 0:2-0:5 Note: The purpose of the status channel training sequence is for the deskew of status and clock signals and for ...
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IDT IDT88K8483 CAL_SEL I_CSW_EN I_DIP_CSW I_CSW_EN SPI-4 Ingress Fill Level Register Read / Field Bits Write FILL_CUR R 0:0-0:5 SPI-4 Ingress Fill Level Register (Block base=0x0300, Register offset=0x0B-0x0C) ...
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IDT IDT88K8483 SPI-4 Ingress WATERMARK Register Read / Field Bits Write WATERMARK R/W 0:0-0:4 Note:(1) 0x1F is the highest watermark that can be set, meaning that the ingress buffer will be full before backpressure will be initiated on a SPI-4 ...
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IDT IDT88K8483 SPI-4 Egress Calendar 1 Table. Read / Field Bits Write LP R/W 0:0-0:7 SPI-4 Egress Calendar 1 Table (Block Base=0x0600, Register Offset=0x00-0x3F/0x7F) Table 74 There are 128 table entries for SPI-4 main egress and 64 table entries for ...
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IDT IDT88K8483 SPI-4 Egress Configuration Register Read / Field Bits Write E_INSYNC_THR R/W 0:0-0:4 E_CLK_EDGE R/W 0:5 E_LOW R/W 0:6 NOSTAT R/W 0:7 E_OUTSYNC_THR R/W 1:0-1:3 Note: Please refer to SPI-4 Ingress State Machine (p. 44) for an illustration of ...
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IDT IDT88K8483 SPI-4 Egress Calendar 0 Configuration Register Read / Field Bits Write E_CAL_M R/W 0:0-0:7 E_CAL_LEN R/W 1:0-1:6 Note the E_CSW_EN bit in SPI-4 Egress Calendar Switch Control Register (p. 116) calendar sequence is repeated before a ...
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IDT IDT88K8483 SPI-4 Egress Status Register Read / Field Bits Write E_SYNCV R 0:0 E_DSK_OOR R 0:1 SCLK_AV R 0:2 SPI-4 Egress Status Register (Block Base=0x0800, Register Offset=0x05) Table 79 SPI-4 Egress Diagnostics Register Read / Field Bits Write E_FORCE_TRAIN ...
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IDT IDT88K8483 SPI-4 Egress Calendar Switch Control Register Read / Field Bits Write E_CSW_EN R/W 0:0 CAL_ID R 0:1 E_DIP_CSW R/W 0:2 Note: Refer to the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) for more details about calendar implementation. SPI-4 Egress Calendar ...
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IDT IDT88K8483 SPI-4 Histogram Measure Launch Register Read / Field Bits Write LANE R/W 0:0-0:4 Note: The manual bit alignment is a edge transition histogram measure process. Please refer to Figure 15(Ingress block diagram) and subsequent description for histogram overview. ...
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IDT IDT88K8483 SPI-4 Bit Alignment Result Register Read / Field Bits Write TAP[7:0] R/W 0:0-0:7 Note: Please refer to SPI-4 Ingress Block Diagram (p. 43) and SPI-4 Egress State Block Diagram (p. 46) for bit alignment overview. Table 88 SPI-4 ...
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IDT IDT88K8483 SPI-4 Egress Data Clock Timing Register Read / Field Bits Write DCTC[0:3] R/W 0:0-0:3 Table 91 SPI-4 Egress Data Clock Timing Control (BlockBase=0x0900, Register Offset=0x2C) SPI-4 Egress Status Timing Register Read / Field Bits Write STC0[0:1] R/W 0:0-0:1 ...
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IDT IDT88K8483 SPI-4 Egress Status Clock Timing Register Read / Field Bits Write SCTC[0:3] R/W 0:0-0:3 SPI-4 Egress Status Clock Timing Control (Block Base=0x0900, Register Offset=0x2E) Table 93 Packet Fragment Processor (PFP) Registers PFP Buffer Segment Assign Table Read / ...
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IDT IDT88K8483 PFP Packet Length Thresholds Read / Field Bits Write LEN_MIN R/W 0:0-0:7 Reserved R/W 1:0-1:7 LEN_MAX R/W 2:0-3:5 Table 95 PFP Packet Length Thresholds There are 64 registers in this table, one for each LID. PFP Queue Diagnose ...
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IDT IDT88K8483 PFP Egress Burst Size Table Read / Field Bits Write MAX_BURST_S R/W 0:0-0:3 MAX_BURST_H R/W 0:4-0:7 Note: The MAX_BURST_H and MAX_BURST_S values relate to MaxBurst2 and MaxBurst1 parameters in the OIF SPI-4 implementation agreement (OIF-SPI-4- 02.1). Table 98 ...
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IDT IDT88K8483 PFP Egress Packet Mode Control Registers Read / Field Bits Write PKT_MODE R/W 0:0 EBP_EN R/W 0:1 Table 100 PFP Egress Packet Mode Control Register (Block Base=0x1600/0x1E00, Register Offset=0x00-0x3F) There are 64 registers, one for each LID. PFP ...
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IDT IDT88K8483 PFP Queue Weighting Enable Register Read / Field Bits Write WEIGHT_EN R/W 0:0 Note: Please refer to page 52 for a detailed explanation of PFP priority and scheduling. Table 103 PFP Queue Weighting Enable Register Reset Length State ...
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IDT IDT88K8483 PFP Flow Control Register Read / Field Bits Write CREDIT_EN R/W 0:0 BURST_EN R/W 0:1 Table 104 PFP Flow Control Register (Block Base=0x1700/0x1F00, Register Offset=0x03) PFP Test Register Read / Field Bits Write REPEAT R/W 0:0 SINGLE_REP R/W ...
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IDT IDT88K8483 PFP Ingress Status Monitor Register - 1 Read / Field Bits Write STATUS[0] R 0:0-0:1 STATUS[1:15] R 0:2-3:7 Note: (1) The status has the same definition as described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) [MSB, LSB] Status ...
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IDT IDT88K8483 PFP Egress Status Monitor Register - 1 Read / Field Bits Write STATUS[0:15] R 0:0-3:7 Note: (1) The egress status has the same definition as described in the OIF SPI-4 implementation agreement (OIF-SPI-4-02.1) and is shown in tus ...
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IDT IDT88K8483 PFP Maximum Packet Length Register Read / Field Bits Write MAX_LEN R/W 0:0-0:5 Table 115 PFP Maximum Packet Length Register (Block Base=0x1700/0x1F00, Register Offset=0x0E) Reset Length State 6 6 This indicates the maximum packet length of the PFP. ...
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IDT IDT88K8483 Auxiliary Registers Auxiliary Interface Enable Register Read / Field Bits Write AUX_EN R/W 0:0 AUX_PDN R/W 0:1 1 Note: The interface has to be configured before enabling it.This is done in Auxiliary Interface Configuration Register (p. 129) 2 ...
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IDT IDT88K8483 Auxiliary Clock Monitor Status Register) Read / Field Bits Write NCLKAV R 0:0 PCLKAV R 0:1 Note: Refer to Table 2 “Pin Description” on page 28 for a brief description of the QDR-II clocks. Table 120 Auxiliary Clock ...
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IDT IDT88K8483 External Memory Test Results Register Read / Field Bits Write TEST_DONE R 0:0 ERROR R 0:1 Table 122 External Memory Test Results Register Auxiliary Early Backpressure Threshold Register Read / Field Bits Write EBP_THR R/W 0:0-1:5 Table 123 ...
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IDT IDT88K8483 Auxiliary Automatic Impedance Matching Control Register Read / Field Bits Write AUTO_MEASURE R/W 0:0 Note: This register is used for diagnostic purpose only. Table 126 Auxiliary Automatic Impedance Matching Control Register (Block Base=0x0A00, Register Offset=0x0F) Auxiliary Synchronization Status ...
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IDT IDT88K8483 Auxiliary Initialization Control Register Read / Field Bits Write INIT_TRIG R/W 0:0 AUTO_SYNCH R/W 0:1 Table 128 Auxiliary Initialization Control Register PRGD Registers Enable Control Register Read/ Field Bits Write GEN R/W 0:0 DEN R/W 0:1 Table 129 ...
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IDT IDT88K8483 Packet Length Register Read/ Field Write P_LEN R/W 0:0 - 1:5 Table 133 Packet Length Register (Block Base=0x0B00, Register Offset=0x03) Burst Size Register Field Read/Write BURST_S R/W Table 134 Burst Size Register (Block Base=0x0B00, Register Offset=0x04) Random Control ...
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IDT IDT88K8483 LID Register Read/ Field Write LID R/W Synchronization Register Read/ Field Write SYNCV R/W 0:0 SYNCI R/W 0:1 Note: (1)The out of sync status can be due to any one of 3 reasons. a) Resetting the device. b) ...
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IDT IDT88K8483 PMON Event Interrupt Indication Register Read / Field Bits Write T_INACT_I R/W 0:0 M_INACT_I R/W 0:1 TM_ISOP_I R/W 0:2 TM_IEOP_I R/W 0:3 MT_ISOP_I R/W 0:4 MT_IEOP_I R/W 0:5 TM_PKTCD_I R/W 0:6 MT_PKTCD_I R/W 0:7 T_LOCKUN_I R/W 1:0 M_LOCKUN_I ...
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IDT IDT88K8483 Read / Field Bits Write T_SCLKLOS_I R/W 1:3 M_DCLKLOS_I R/W 1:4 M_SCLKLOS_I R/W 1:5 T_DIP2_I R/W 1:6 T_DIP4_I R/W 1:7 T_BUSERR_I R/W 2:0 T_ISYNC_I R/W 2:1 T_ESYNC_I R/W 2:2 M_DIP2_I R/W 2:3 M_DIP4_I R/W 2:4 Table 139 PMON ...
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IDT IDT88K8483 Read / Field Bits Write M_BUSERR_I R/W 2:5 M_ISYNC_I R/W 2:6 M_ESYNC_I R/W 2:7 Table 139 PMON Event Interrupt Indication Register (Block Base=0x0F00, Register Offset=0x00) Reset Length State 1 0 Main SPI4 bus error event. Read 1: Indicates ...
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IDT IDT88K8483 PMON Event Interrupt Enable Register Read / Field Bits Write T_INACT_EN R/W 0:0 M_INACT_EN R/W 0:1 TM_ISOP_EN R/W 0:2 TM_IEOP_EN R/W 0:3 MT_ISOP_EN R/W 0:4 MT_IEOP_EN R/W 0:5 TM_PKTCD_EN R/W 0:6 MT_PKTCD_EN R/W 0:7 T_LOCKUN_EN R/W 1:0 M_LOCKUN_EN ...
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IDT IDT88K8483 Read / Field Bits Write T_DIP4_EN R/W 1:7 T_BUSERR_EN R/W 2:0 T_ISYNC_EN R/W 2:1 T_ESYNC_EN R/W 2:2 M_DIP2_EN R/W 2:3 M_DIP4_EN R/W 2:4 M_BUSERR_EN R/W 2:5 M_ISYNC_EN R/W 2:6 M_ESYNC_EN R/W 2:7 Note: Writing any ...
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IDT IDT88K8483 PMON Buffer M-T Overflow Indication Register Read / Field Bits Write OVERFLOW[31:0] R/W 0:0-3:7 Table 142 PMON Buffer M-T Overflow Indication Register (Block Base=0x0F00, Register Offset=0x04-0x05) There are 2 registers. PMON Buffer T-M Overflow Interrupt Control Register Read ...
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IDT IDT88K8483 PMON Buffer Overflow Source Register Read / Field Bits Write TM_OVF R 0:0 MT_OVF R 0:1 Table 145 PMON Buffer Overflow Source Register (Block Base=0x0F00, Register Offset=0x0A) PMON T-M Inactive Transfer LP Field Register Read / Field Bits ...
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IDT IDT88K8483 PMON M-T Illegal SOP Event LID Field Register Read / Field Bits Write LID R 0:0-0:5 Table 150 PMON M-T Illegal SOP Event Field Register (Block Base=0x0F00, Register Offset=0x0F) PMON M-T Illegal EOP Event LID Field Register Read ...
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IDT IDT88K8483 PMON Per LID Counter Table Register Length Offset 6n+1 24 0x6n+2 24 0x6n+3 24 0x6n+4 24 0x6n+5 Note: (1) In the register offset column ‘n’ refers to the LID number, with n between ...
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IDT IDT88K8483 Miscellaneous Registers PMON Timebase Control Register Read / Field Bits Write INTERNAL R/W 0:0 TIMER R/W 0:1 MANUAL R/WC 0:2 PMON Timebase Control Register Table 156 Manual Bit PMON 1ms Timer Register Read / ...
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IDT IDT88K8483 GPIO Level Register Read / Field Bits Write LEVEL R/W 0:0 GPIO Level Register (Block Base=0x8B00, Register Offset=0x13-0x15) Table 160 There are 3 registers. GPIO Link Table Read / Field Bits Write ADDRESS R/W 0:0- 1:7 BIT R/W ...
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IDT IDT88K8483 Electrical and Thermal Specification Absolute Maximum Ratings Parameter Core Digital Supply Voltage I/O Digital Supply Voltage for LVDS I/O Digital Supply Voltage for HSTL I/O Digital Supply Voltage for LVDS I/O Digital Supply Voltage for HSTL I/O Digital ...
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IDT IDT88K8483 Parameter Reference for Termination I/O Reference for LDVS I/O Reference for HSTL Thermal Characteristics Parameter Maximum Power Dissipation total Maximum Power Dissipation of core Maximum Power Dissipation of each LVDS SPI-4 Interface I/O Maximum Power Dissipation of HSTL ...
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IDT IDT88K8483 DC Characteristics Parameter CMOS I/O Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage Schmitt Trigger Input - Low-Level Voltage Schmitt Trigger Input - High-Level Voltage I/O Off State Leakage Current Pull-Up Resistor in Input/Bidirectional ...
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IDT IDT88K8483 Parameter Differential Output Short Circuit Cur- rent HSTL I/O Low-Level Input Voltage High-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage AC Characteristics Parameter Clock Interface. Reference clock (SPI4M_RCLK, SPI4B_RCLK, SPI4A_RCLK) frequency Reference clock Duty cycle Reference clock ...
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IDT IDT88K8483 Parameter DCLK clock duty cycle SCLK clock duty cycle Fall time (20%, 80%) Rise time (20%, 80%) Differential Skew ( DCLK and SCLK peak to peak Jitter DAT and CTL peak to peak Jitter Clock-to-Output Propagation ...
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IDT IDT88K8483 Parameter MCU Interface - Motorola mode - non multiplexed bus (MPM=0). Write Cycle. . Access p.155 Internal master clock (MCLK) frequency (defined by the main clock generator) Write cycle time Valid DSB width Delay from DSB to valid ...
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IDT IDT88K8483 Parameter SCLK Frequency Min. /CS High Time /CS Setup Time /CS Hold Time Clock Disable Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Output Delay Output Disable Time JTAG Interface. Figure 54 JTAG ...
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IDT IDT88K8483 K /K tKWV tKAV / D00 tKDV tKDV / D01 D10 D11 Figure 46 Auxiliary Interface - QDR-II / Generic - Write Access tKRV tKAV A Figure 47 ...
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IDT IDT88K8483 ...
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IDT IDT88K8483 CSB+_RDB A[x:0] Read[7:0] Note: WRB should be tied to high WRB+CSB A[x:0] Write[7:0] Note: RDB should be tied to high tRC tRDW tAV Valid Address tPRD Figure 50 MCU Interface - Intel Mode - Read Access tRC tRDW ...
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IDT IDT88K8483 A_ESCLK A_ESCLK VDDT33 DAT2 DAT1 DAT0 _L_P _L_N A A_ESTA_ A_ESTA_ VSS VSS DAT3 ADR5 WRB L_P[1] L_N[1] B A_ESTA_ A_ESTA_ DAT6 DAT5 DAT4 ADR3 RDB L_P[0] L_N[0] C A_ESCLK A_ESTA_ ...
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IDT IDT88K8483 /CS SCLK SDI High Impedance SDO TCK TDI TMS TDO tCSS tCLH tCLL tDIH tDIS Valid Input t PD Valid Output Figure 53 Serial Peripheral Interface t tStdi Htdi tStms t Htms Figure 54 JTAG Interface 158 of ...
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IDT IDT88K8483 Mechanical data Figure 55 BR 672 FCBG Package Outline, RoHS compliant 159 of 162 October 20, 2006 ...
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IDT IDT88K8483 Document Revision History The document revision history is described in Table 169. Issue Date 1.0 10/20/2006 General Release Description Table 169 Document Revision History 160 of 162 October 20, 2006 ...
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... IDT IDT88K8483 Ordering Information The ordering information is described in Table 170. Device Code IDT88K8483BRI IDT88K8483 SPI-4 Exchange, Industrial temperature, RoHS 6 IDT88K8483BLI IDT88K8484 SPI-4 Exchange, Industrial temperature, RoHS 5 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 Product Table 170 Ordering Information ...
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IDT IDT88K8483 162 of 162 October 20, 2006 ...