IDT88P8342BHGI IDT, Integrated Device Technology Inc, IDT88P8342BHGI Datasheet - Page 8

• Manufacturer Part Number: IDT88P8342BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8342BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8342BHGI

1. INTRODUCTION
intended for use in optical line cards, Ethernet transport, and multi-service
switches. The SPI-3 and SPI-4 interfaces are defined by the Optical
Interworking Forum.
device between network processor units, multi-gigabit framers and PHYs, and
switch fabric interface devices.
DATA PATH OVERVIEW
the device.
the dual SPI-3 ingress to SPI-4 egress path, and the SPI-4 ingress to dual SPI-
3 egress path. SPI-3 and SPI-4 burst sizes are separately configurable.
TYPICAL APPLICATION
Exchange between optical ports and two NPU/Traffic Managers
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
The IDT88P8342 device is a dual SPI-3 to single SPI-4 exchange
The device can be used as a rate adapter, a switch, or an aggregation
Figure 1. Data Path Diagram shows an overview of the data path through
In normal operation, there are two paths through the IDT88P8342 device:
OC-48/
4xOC-12/
16xOC-3
SPI-3
SPI-3
Multi-Rate
SONET
Framer
Figure 1. Typical application: optical port and two NPUs
I/F
I/F
SPI-4
SPI-3 ingress to SPI-4 egress
SPI-4 ingress to SPI-3 egress
Memory
Memory
IDT88P8342
Figure 2. Data Path Diagram
8
3 interface and are received by the SPI-3 interface block. The fragments are
mapped to a SPI-4 address and stored in memory allocated at the SPI-3 level
until such a time that the Packet Fragment Processor determines that they are to
be transmitted on the SPI-4 interface. The data is transferred in bursts, in line with
the OIF SPI-4 implementation agreement, to the SPI-4 interface block, and are
transmitted on the SPI-4 interface.
interface and are received by the SPI-4 interface block. The SPI-4 address is
translated to a SPI-3 address, and the data contained in the bursts are stored
in memory allocated at the SPI-3 level until such a time that the Packet Fragment
Processor determines that they are to be transmitted on the SPI-3 interface. The
data is transferred in packet fragments, in line with the OIF SPI-3 implementation
agreement, to the SPI-3 interface block, and are transmitted on the SPI-3
interface.
In the SPI-3 ingress to SPI-4 egress path, data enter in fragments on the SPI-
In the SPI-4 ingress to SPI-3 egress path, data enter in bursts on the SPI-4
I/F
SPI-3
SPI-3
6371 drw03
SPI-4
NPU
NPU
INDUSTRIAL TEMPERATURE RANGE
Processor
Control
PCI
6371 drw02
APRIL 10, 2006