IDT88P8342BHGI IDT, Integrated Device Technology Inc, IDT88P8342BHGI Datasheet - Page 5

• Manufacturer Part Number: IDT88P8342BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8342BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8342BHGI

IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
List of Tables
Table 1 – I/O types .......................................................................................................................................................................................................... 9
Table 2 – SPI-3 ingress interface pin definition .................................................................................................................................................................. 9
Table 3 – SPI-3 egress interface pin definition ................................................................................................................................................................ 10
Table 4 – SPI-3 status interface pin definition .................................................................................................................................................................. 10
Table 5 – SPI-4 ingress interface definition ..................................................................................................................................................................... 11
Table 6 – SPI-4 egress interface definition ...................................................................................................................................................................... 11
Table 7 – Parallel microprocessor interface .................................................................................................................................................................... 12
Table 8 – Serial microprocessor interface (serial peripheral interface mode) ................................................................................................................... 12
Table 9 – Miscellaneous ................................................................................................................................................................................................ 12
Table 10 – Both attached devices start from reset status .................................................................................................................................................. 20
Table 11 – Ingress out of synch, egress in synch ........................................................................................................................................................... 20
Table 12 – Ingress in synch, egress out of synch ........................................................................................................................................................... 20
Table 13 - DIRECTION code assignment ...................................................................................................................................................................... 26
Table 14 – CK_SEL[3:0] input pin encoding ................................................................................................................................................................... 39
Table 15 - Zero margin SPI-3 timing budget ................................................................................................................................................................... 43
Table 16 - Margin check for SPI-3 timing ........................................................................................................................................................................ 43
Table 17 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46
Table 18 - Bit order within a 32-Bit data register ............................................................................................................................................................. 46
Table 19 - Bit order within an 8-Bit data register ............................................................................................................................................................. 46
Table 20 - Bit order within a 16-Bit address register ....................................................................................................................................................... 47
Table 21 - Bit order within an 8-Bit control register .......................................................................................................................................................... 47
Table 22 - Module base address (Module_base) ........................................................................................................................................................... 47
Table 23 - Indirect access block bases for Module A and Module B ................................................................................................................................. 47
Table 24 - Indirect access block bases for common module ............................................................................................................................................ 48
Table 25 - Indirect access data registers (direct accessed space) at 0x30 to 0x33 .......................................................................................................... 48
Table 26 - Indirect access address register (direct accessed space) at 0x34 to 0x35 ...................................................................................................... 48
Table 27 - Indirect access control register (direct accessed space) at 0x3F ..................................................................................................................... 48
Table 28 - Error coding table ......................................................................................................................................................................................... 49
Table 29 - Direct mapped Module A and Module B registers .......................................................................................................................................... 50
Table 30 - Direct mapped other registers ....................................................................................................................................................................... 50
Table 31 - SPI-3 data capture control register (registers 0x00 and 0x08) ....................................................................................................................... 50
Table 32 - SPI-3 data capture register (registers 0x01 and 0x09) .................................................................................................................................. 50
Table 33 - SPI-4 data insert control register (registers 0x02 and 0x0A) .......................................................................................................................... 51
Table 34 - SPI-4 data insert register (registers 0x03 and 0x0B) ..................................................................................................................................... 51
Table 35 - SPI-4 data capture control registers (registers 0x04 and 0x0C) ..................................................................................................................... 51
Table 36 - SPI-3 data insert control register (registers 0x05 and 0x0D) .......................................................................................................................... 51
Table 37 - SPI-4 data capture register (registers 0x06 and 0x0E) .................................................................................................................................. 51
Table 38 - SPI-3 data insert register (registers 0x07 and 0x0F) ..................................................................................................................................... 51
Table 39 - Software reset register (0x20 in the direct accessed space) ........................................................................................................................... 52
Table 40 - SPI-4 status register (0x22 in the direct accessed space) ............................................................................................................................... 52
Table 41 - SPI-4 enable register (0x23 in the direct accessed space) ............................................................................................................................. 52
Table 42 - Module status register (0x24 and 0x25 in the direct accessed space) ............................................................................................................ 53
Table 43 - Module enable register (0x28 and 0x29 in the direct accessed space) .......................................................................................................... 53
Table 44 - Primary interrupt status register (0x2C in the direct accessed space) ............................................................................................................. 54
Table 45 - Secondary interrupt status register (0x2D in the direct accessed space) ........................................................................................................ 54
Table 46 - Primary interrupt enable register (0x2E in the direct accessed space) ............................................................................................................ 55
Table 47 - Secondary interrupt enable register (0x2F in the direct accessed space) ....................................................................................................... 55
Table 48 - Module A/B indirect register ........................................................................................................................................................................... 56
Table 49 - SPI-3 ingress LP to LID map ......................................................................................................................................................................... 57
Table 50 - SPI-3 general configuration register (register_offset=0x00) ............................................................................................................................ 57
Table 51 - SPI-3 ingress configuration register (register_offset=0x01) ............................................................................................................................. 58
Table 52 - SPI-3 ingress fill level register (register_offset=0x02) ..................................................................................................................................... 58
Table 53 - SPI-3 ingress max fill level register (register_offset=0x03) .............................................................................................................................. 58
Table 54 - SPI-3 egress LID to LP map ......................................................................................................................................................................... 58
Table 55 - SPI-3 egress configuration register (register_offset=0x00) ............................................................................................................................. 59
Table 56 - SPI-4 ingress to SPI-3 egress flow control register (register_offset=0x01) ...................................................................................................... 59
APRIL 10, 2006
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