FDMF8705 Fairchild Semiconductor, FDMF8705 Datasheet - Page 9

• Manufacturer Part Number: FDMF8705
• Description: IC MODULE DRIVER/FET POWER88-56
• Manufacturer: Fairchild Semiconductor
• Type: Step-Down (Buck)r

Specifications of FDMF8705

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Current - Output: 18A
• Frequency - Switching: 500kHz
• Voltage - Input: 12V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 56-MLP
• Power - Output: 6.25W
• Supply Voltage (min): 6.4 V
• Supply Current: 8 mA
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FDMF8705TR

FDMF8705 Rev. C
Description of Operation
Circuit Description
The FDMF8705 is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 500KHz.
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground
referenced low R
is internally connected between VCIN and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB = 0V), LDRV
is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (C
start-up, VSWH is held at PGND, allowing C
VCIN through the internal diode. When the PWM input goes
high, HDRV will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C
delivered to Q1's gate. As Q1 turns on, VSWH rises to V
forcing the BOOT pin to V
sufficient VGS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling HDRV to VSWH. C
recharged to VCIN when VSWH falls to PGND. HDRV output is
in phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
DS(ON)
N-channel MOSFET. The bias for LDRV
IN
V
HDRV-SW
SW
PWM
LDRV
LDRV / HDRV
DISB
IH(PWM)
+V
C(BOOT)
t
PDH(HDRV)
V
IL(DISB)
, which provides
BOOT
1.2V
Figure 25. Adaptive Gate Drive Timing
BOOT
to charge to
BOOT
t
PDL(LDRV)
Figure 24. Output Disable Timing
BOOT
). During
is then
and
t
PDL(DISB)
IN
,
t
V
PDL(HDRV)
9
IL(PWM)
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 24 and 25
for the relevant timing waveforms.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the LDRV pin. When the PWM signal goes HIGH, Q2 will
begin to turn OFF after some propagation delay (t
Once the LDRV pin is discharged below ~1.2V, Q1 begins to
turn ON after adaptive delay t
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the SW
pin. When the PWM signal goes LOW, Q1 will begin to turn OFF
after some propagation delay (t
falls below ~2.2V, Q2 begins to turn ON after adaptive delay
t
Additionally, V
discharged below ~1.2V, a secondary adaptive delay is initiated,
which results in Q2 being driven ON after t
of SW state. This function is implemented to ensure C
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and SW voltage does not fall
below the 2.2V adaptive threshold. Secondary delay t
is longer than t
pdh(LDRV)
V
t
IH(DISB)
PDH(LDRV)
.
2.2V
PDH(LDRV)
GS
of Q1 is monitored. When V
t
PDH(DISB)
.
PDH(HDRV)
PDL(HDRV)
.
). Once the VSWH pin
PDH(LDRV),
www.fairchildsemi.com
PDL(LDRV)
regardless
PDH(HDRV)
GS(Q1)
BOOT
is
is
).