LTC3703EGN Linear Technology, LTC3703EGN Datasheet - Page 14

IC BUCK/BOOST SYNC ADJ 5A 16SSOP

LTC3703EGN

Manufacturer Part Number
LTC3703EGN
Description
IC BUCK/BOOST SYNC ADJ 5A 16SSOP
Manufacturer
Linear Technology
Type
Step-Down (Buck), Step-Up (Boost)r
Datasheet

Specifications of LTC3703EGN

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.8 ~ 93 V
Current - Output
5A
Frequency - Switching
100kHz ~ 600kHz
Voltage - Input
9.3 ~ 100 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-

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APPLICATIONS INFORMATION
LTC3703
breakdown specifi cation. Since many high voltage MOSFETs
have higher threshold voltages (typically, V
the LTC3703 is designed to be used with a 9V to 15V gate
drive supply (DRV
For maximum effi ciency, on-resistance R
capacitance should be minimized. Low R
conduction losses and low input capacitance minimizes
transition losses. MOSFET input capacitance is a combi-
nation of several components but can be taken from the
typical “gate charge” curve included on most data sheets
(Figure 9).
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The fl at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is fl at) is specifi ed for a given V
voltage, but can be adjusted for different V
multiplying by the ratio of the application V
specifi ed V
is to take the change in gate charge from points a and b
on a manufacturers data sheet and divide by the stated
V
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specifi ed on MOSFET
data sheets. C
defi nitions of these parameters are not included.
14
DS
V
voltage specifi ed. C
GS
C
MILLER
DS
a
Figure 9. Gate Charge Characteristic
MILLER EFFECT
values. A way to estimate the C
RSS
= (Q
Q
IN
B
CC
and C
– Q
pin).
A
)/V
b
DS
MILLER
OS
are specifi ed sometimes but
is the most important se-
V
+
GS
V
DS(ON)
DS(ON)
DS
DS
GS(MIN)
MILLER
to the curve
voltages by
+
minimizes
and input
V
3703 F09
DS
DS
V
IN
≥ 6V),
drain
term
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given
by:
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
where δ is the temperature dependency of R
is the effective top driver resistance (approximately 2Ω at
V
in drain potential in the particular application. V
the data sheet specifi ed typical gate threshold voltage
specifi ed in the power MOSFET data sheet at the specifi ed
drain current. C
the gate charge curve from the MOSFET data sheet and
the technique described above.
Both MOSFETs have I
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
the high current effi ciency generally improves with larger
MOSFETs, while for V
increase to the point that the use of a higher R
with lower C
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short circuit when the synchronous switch is on close
to 100% of the period.
GS
Main Switch Duty Cycle
P
P
Synchronous S
MAIN
SYNC
= V
MILLER
=
=
V
V
V
MILLER
IN
V
V
OUT
IN
IN
CC
), V
2
MILLER
V
I
MAX
IN
(
V
2
IN
I
MAX
1
OUT
V
actually provides higher effi ciency. The
w w itch Duty Cycle
TH IL
is the drain potential and the change
2
(
IN
R losses while the topside N-channel
R R
( )
is the calculated capacitance using
)
(
> 25V, the transition losses rapidly
DR
I
2
MAX
(
1
+
)(
+
C
=
V
) (
δ
2
MILLER
TH IL
V
)
R
1
V
1 δ
OUT
( )
IN
+
DS ON
(
⎥ ⎥
)
) •
R
( )
=
f
DS N
)
V
+
(
IN
0
V
)
DS(ON)
IN
V
DS(ON)
OUT
IN
TH(IL)
device
< 25V,
, R
3703fb
DR
is

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