FDMF8704V Fairchild Semiconductor, FDMF8704V Datasheet - Page 4

• Manufacturer Part Number: FDMF8704V
• Description: IC MOD DVR/FET W/VREG 56MLP 8X8
• Manufacturer: Fairchild Semiconductor
• Type: Step-Down (Buck)r

Specifications of FDMF8704V

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 3.2 V
• Current - Output: 32A
• Frequency - Switching: 1MHz
• Voltage - Input: 7 ~ 20 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 56-MLP
• Power - Output: 10W
• Supply Voltage (min): 4.5 V
• Supply Current: 50 mA
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Drivers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDMF8704VTR

FDMF8704V Rev. G
Functional Block Diagram
Functional Description
The FDMF8704V is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 1MHz.
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground refer-
enced low R
internally connected between VCIN and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB = 0V), LDRV
is held low.
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
external diode and external bootstrap capacitor (C
start-up, VSWH is held at PGND, allowing C
V
high, HDRV will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from C
delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN,
forcing the BOOT pin to VIN + V
sufficient V
cycle, Q1 is turned off by pulling HDRV to VSWH. C
recharged to V
in phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
CIN
through the internal diode. When the PWM input goes
GS
DS(ON)
PWM
VCIN
DISB
enhancement for Q1. To complete the switching
CIN
when VSWH falls to PGND. HDRV output is
N-channel MOSFET. The bias for LDRV is
REGFB
REGOUT
C(BOOT)
Figure 3. Functional Block Diagram
BOOT
VAUX
, which provide
BOOT
R
to charge to
BOOT
BOOT
). During
REF
is then
R
and
VCIN
HSEN
4
CGND
Adaptive Gate Drive Circuit
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential shoot-
through (cross-conduction) currents. It senses the state of the
MOSFETs and adjusts the gate drive, adaptively, to ensure they
do not conduct simultaneously. Refer to Figure 4 and 5 for the
relevant timing waveforms. To prevent overlap during the low-
to-high switching transition (Q2 OFF to Q1 ON), the adaptive
circuitry monitors the voltage at the LDRV pin. When the PWM
signal goes HIGH, Q2 will begin to turn OFF after some
propagation delay (t
discharged below ~1.2V, Q1 begins to turn ON after adaptive
delay t
transition (Q1 OFF to Q2 ON), the adaptive circuitry monitors
the voltage at the SW pin. When the PWM signal goes LOW, Q1
will begin to turn OFF after some propagation delay
(t
to turn ON after adaptive delay t
Q1 is monitored. When V
secondary adaptive delay is initiated, which results in Q2 being
driven ON after t
function is implemented to ensure C
switching cycle, particularly for cases where the power
converter is sinking current and SW voltage does not fall below
the 2.2V adaptive threshold. Secondary delay t
longer than t
PDL(HDRV)
PDH(HDRV)
BOOT
). Once the VSWH pin falls below ~2.2V, Q2 begins
PDH(LDRV)
. To preclude overlap during the high-to-low
PDH(LDRV)
HDRV
LDRV
.
PDL(LDRV)
Q1
Q2
GS(Q1)
, regardless of SW state. This
PGND
VIN
). Once the LDRV pin is
PDH(LDRV)
is discharged below ~1.2V, a
BOOT
. Additionally, V
VSWH
is recharged each
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PDH(HDRV)
GS
of
is