ISL6755AAZA-T Intersil, ISL6755AAZA-T Datasheet - Page 9

• Manufacturer Part Number: ISL6755AAZA-T
• Description: IC CTRLR PWM FULL-BRDG 20-QSOP
• Manufacturer: Intersil

Specifications of ISL6755AAZA-T

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 16 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-QSOP
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
D
DT
Soft-Start Operation
The ISL6755 features a soft-start using an external capacitor in
conjunction with an internal current source. Soft-start reduces
component stresses and surge currents during start-up.
Upon start-up, the soft-start circuitry limits the error voltage
input (VERR) to a value equal to the soft-start voltage. The
output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the
soft-start period. When the soft-start voltage exceeds the
error voltage, soft-start is completed. Soft-start occurs during
start-up and after recovery from a fault condition. The
soft-start charging period may be calculated as follows:
where t is the charging period in ms and C is the value of the
soft-start capacitor in μF.
The soft-start voltage is clamped to 4.50V with a tolerance of
2%. It is suitable for use as a “soft-started” reference
provided the current draw is kept well below the 70μA
charging current.
The outputs may be inhibited by using the SS pin as a
disable input. Pulling SS below 0.25V forces all outputs low.
An open collector/drain configuration may be used to couple
the disable signal into the SS pin.
Gate Drive
The ISL6755 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50Ω.
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle
peak overcurrent protection which provides fast response.
The cycle-by-cycle peak current limit results in pulse-by-pulse
duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the threshold,
the active output pulse is immediately terminated. This results
in a decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6755 operates
continuously in an overcurrent condition without shutdown.
t
=
=
=
64.3 C
----------- -
T
T
SW
1 D
C
–
⋅
ms
9
(EQ. 4)
(EQ. 5)
(EQ. 6)
ISL6755
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent
protection also maintains flux balance in the transformer by
maintaining duty cycle symmetry between half-cycles. If
voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. The DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. Average current limit will prevent the
instability and allow continuous operation in current limit
provided the control loop is designed with adequate
bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to
the peak current comparator and a sample and hold
averaging circuit. After a 70ns leading edge blanking (LEB)
delay, the current sense signal is actively sampled during the
on time, the average current for the cycle is determined, and
the result is amplified by 4x and output on the IOUT pin. If an
RC filter is placed on the CS input, its time constant should
not exceed ~50ns or significant error may be introduced on
I
Figure 5 shows the relationship between the CS signal and
IOUT under steady state conditions. I
of CS. Figure 6 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external
sine wave. Notice I
circuitry at the termination of the active output pulse.
OUT
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
.
FIGURE 5. CS INPUT vs IOUT
OUT
is updated by the sample and hold
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
OUT
is 4x the average
September 29, 2008
FN6442.1