ISL6755AAZA-T Intersil, ISL6755AAZA-T Datasheet

IC CTRLR PWM FULL-BRDG 20-QSOP

ISL6755AAZA-T

Manufacturer Part Number
ISL6755AAZA-T
Description
IC CTRLR PWM FULL-BRDG 20-QSOP
Manufacturer
Intersil
Datasheet

Specifications of ISL6755AAZA-T

Pwm Type
Voltage/Current Mode
Number Of Outputs
4
Frequency - Max
2MHz
Duty Cycle
100%
Voltage - Supply
9 V ~ 16 V
Buck
No
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 105°C
Package / Case
20-QSOP
Frequency-max
2MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ZVS Full-Bridge PWM Controller with
Average Current Limit
The ISL6755 is a high-performance extension of the Intersil
family of full-bridge ZVS controllers. Like the ISL6753, it
achieves ZVS operation by driving the upper bridge FETs at
a fixed 50% duty cycle while the lower bridge FETS are
trailing-edge modulated with adjustable resonant switching
delays.
Adding to the ISL6753’s feature set is average current
monitoring. The signal may be used for average current
limiting, current sharing circuits and average current mode
control.
This advanced BiCMOS design features low operating
current, adjustable oscillator frequency up to 2MHz,
adjustable soft-start, precision deadtime and resonant delay
control, and short propagation delays. Additionally,
Multi-Pulse Suppression ensures alternating output pulses
at low duty cycles where pulse skipping may occur.
Ordering Information
Pinout
ISL6755AAZA* 6755 AAZ
*Add -T suffix to part number for tape and reel packaging
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
NUMBER
(Note)
PART
MARKING
PART
R E S D E L
C TB U F
R A M P
V E R R
IO U T
R TD
FB 2
FB 1
C T
C S
(20 LD QSOP)
10
1
2
3
4
5
6
7
8
9
TOP VIEW
ISL6755
¬
-40 to +105 20 Ld QSOP M20.15
RANGE
1
TEMP.
(°C)
20
19
18
17
16
15
14
13
12
11
Data Sheet
V R E F
S S
V D D
O U TLL
O U TLR
O U TU L
O U TU R
N /C
G N D
G N D
PACKAGE
(Pb-free)
DWG. #
PKG.
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Adjustable Resonant Delay for ZVS Operation
• Voltage- or Current-Mode Operation
• 3% Current Limit Threshold
• Adjustable Average Current Limit
• 175µA Startup Current
• Supply UVLO
• Adjustable Deadtime Control
• Adjustable Soft-Start
• Adjustable Oscillator Frequency Up to 2MHz
• Tight Tolerance Error Amplifier Reference Over Line,
• 5MHz GBWP Error Amplifier
• Adjustable Cycle-by-Cycle Peak Current Limit
• Fast Current Sense to Output Delay
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
• Buffered Oscillator Sawtooth Output
• Internal Over-Temperature Protection
• Pb-Free (RoHS Compliant)
Applications
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
• Wireless Base Station Power
• File Server Power
• Industrial Power Systems
September 29, 2008
Load, and Temperature
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
ISL6755
FN6442.1

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ISL6755AAZA-T Summary of contents

Page 1

... PART RANGE (Note) MARKING (°C) ISL6755AAZA* 6755 AAZ -40 to +105 20 Ld QSOP M20.15 *Add -T suffix to part number for tape and reel packaging NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...

Page 2

Functional Block Diagram VDD VREF UVLO OVER- TEMPERATURE PROTECTION GND VREF RESDEL IOUT 4X OSCILLATOR CT RTD CTBUF SS 50% PWM STEERING LOGIC PWM SAMPLE + AND HOLD - 1.00V OVER CURRENT COMPARATOR PWM COMPARATOR 80mV VREF + - 0.33 ...

Page 3

Typical Application - High Voltage Input ZVS Full-Bridge Converter VIN+ CR2 R19 Q8A Q8B 400 VDC Q6A Q6B Q4 VIN- T2 CR1 R10 VDD BIAS CR3 T3 Q2 R20 Q5A ...

Page 4

... ISL6755 Thermal Information Thermal Resistance (Typical) 20 Lead QSOP (Note 1 0.3V REF Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp < 20V, RTD = 10.0kΩ 470pF TEST CONDITIONS LOAD ...

Page 5

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. A Temperature limits established ...

Page 6

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < +25°C; Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. A Temperature limits established ...

Page 7

Typical Performance Curves 1.02 1.01 1 0.99 0.98 -40 -25 - TEMPERATURE (¬¨Ð FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE 4 1- 1000pF CT = 1000pF CT = 680pF CT = 680pF CT = 470pF CT ...

Page 8

RC network to produce the desired sawtooth waveform. OUTUL and OUTUR - These outputs control the upper bridge FETs and operate at a fixed 50% duty cycle in alternate sequence. OUTUL controls the upper left FET and OUTUR ...

Page 9

The maximum duty cycle, D, and percent deadtime, DT, can be calculated from ----------- - – Soft-Start Operation The ISL6755 features a soft-start using an external capacitor in conjunction with ...

Page 10

CHANNEL 1 (YELLOW): OUTLL CHANNEL 2 (RED): OUTLR CHANNEL 3 (BLUE): CS CHANNEL 4 (GREEN): IOUT FIGURE 6. DYNAMIC BEHAVIOR IOUT The average current signal on I remains accurate OUT provided that the output inductor current is ...

Page 11

The peak overcurrent behavior is similar to most other PWM controllers. If the peak current exceeds 1.0V, the active output pulse is terminated immediately. If voltage-mode control is used in a bridge topology, it should be noted that peak current ...

Page 12

Adding the external ramp to the current feedback signal is the more popular method. From the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, Fm, without slope compensation ...

Page 13

CS pin as shown in Figure 10 FIGURE 10. ADDING SLOPE COMPENSATION Assuming the designer has selected values for the RC ...

Page 14

Equation 24 becomes: ( Δ ⋅ – Ω ------------------------------------------------------------ - R9 = ΔV V – The buffer transistor used to create the external ramp from CT should have a sufficiently ...

Page 15

This condition persists through the remainder of the half-cycle. During the period when CT discharges, also referred to as the deadtime, the upper switches toggle. Switch UL turns off and switch UR turns on. The actual timing of the upper ...

Page 16

VIN VIN- FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT TRANSITION The first power transfer period commences when switch LR closes and the cycle repeats. The ZVS transition requires that the ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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