CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 9

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL is
disabled by applying ground to the DOFF pin. When the DLL is
turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
Application Example
Truth Table
The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows.
Notes
Document Number: 001-06550 Rev. *D
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle;
read data on consecutive K and K rising edges.
NOP: No Operation
Standby: Clock Stopped
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
symmetrically.
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
MASTER
BUS
Source CLK
Source CLK
Cycle Start
Addresses
Operation
R/W
DQ
DQ
A
SRAM#1
LD R/W
Figure 1. Application Example
CQ/CQ
K
Stopped
ZQ
K
L-H
L-H
L-H
K
R = 250ohms
the
QDRII/DDRII/QDRII+/DDRII+. The DLL is reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock at the
desired frequency. During power up, when the DOFF is tied
HIGH, the DLL gets locked after 2048 cycles of stable clock.
LD
H
L
L
X
application
R/W
H
L
X
X
DQ
D(A) at K(t + 1) ↑
Q(A) at K(t + 2) ↑
High Z
Previous State
A
note,
SRAM#2
LD R/W
[3, 4, 5, 6, 7, 8]
DQ
DLL
CQ/CQ
K
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
ZQ
K
D(A+1) at K(t + 1) ↑
Q(A+1) at K(t + 2) ↑
High Z
Previous State
Considerations
R = 250ohms
DQ
Page 9 of 27
in
[+] Feedback