CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 13

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDCODE
A vendor specific 32-bit code is loaded into the Instruction
register by the IDCODE instruction. It also places the Instruction
register between the TDI and TDO pins and enables shifting the
IDCODE out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into the
Instruction register upon power up or whenever the TAP
controller is in a Test-Logic-Reset state.
SAMPLE Z
The Boundary Scan register is connected between the TDI and
TDO pins when the TAP controller is in a Shift-DR state by the
SAMPLE Z instruction. The SAMPLE Z command puts the
output bus into a High Z state until the next command is issued
during the Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
Instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the Boundary Scan register.
The TAP controller clock only operates at a frequency up to 20
MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state an
input or output may undergo a transition. The TAP then tries to
capture a signal while in transition (metastable state). This does
not harm the device but there is no guarantee as to the value that
is captured. Repeatable results are not possible.
To guarantee that the Boundary Scan register captures the
correct value of a signal, the SRAM signal is stabilized long
enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the Boundary Scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the Boundary
Scan register between the TDI and TDO pins.
An initial data pattern is placed at the latched parallel outputs of
the Boundary Scan register cells before the selection of another
boundary scan test operation by PRELOAD.
Document Number: 001-06550 Rev. *D
CS
and t
CH
). The SRAM clock input is not captured
The shifting of data for the SAMPLE and PRELOAD phases
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the Instruction
register and the TAP is placed in a Shift-DR state, the Bypass
register is placed between the TDI and TDO pins. The advantage
of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
EXTEST
The preloaded data is driven out through the system output pins
by the EXTEST instruction. This instruction also selects the
Boundary Scan register connected for serial access between the
TDI and TDO in the Shift-DR controller state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
The Boundary Scan register has a special bit located at bit 108
called the “extest output bus tri-state”. When this scan cell is
latched into the Preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the Preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions
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