CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 10

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Write Cycle Descriptions
The write cycle description table for CY7C1546V18 and CY7C1548V18 follows.
Write Cycle Descriptions
The write cycle description table for CY7C1557V18 follows.
Note
Document Number: 001-06550 Rev. *D
9. Assumes a write cycle is initiated as per the
BWS
NWS
BWS
H
H
H
H
cycle, as long as the setup and hold requirements are met.
H
H
L
L
L
L
L
L
0
0
0
/
BWS
NWS
L–H
L–H
H
H
H
H
L
L
L
L
K
–
–
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
L–H
L–H
K
–
–
L–H During the data portion of a write sequence :
L–H During the data portion of a write sequence :
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence :
K
–
–
–
–
During the data portion of a write sequence, the single byte (D
During the data portion of a write sequence, the single byte (D
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
During the data portion of a write sequence :
CY7C1546V18 − both nibbles (D
CY7C1548V18 − both bytes (D
CY7C1546V18 − both nibbles (D
CY7C1548V18 − both bytes (D
During the data portion of a write sequence :
CY7C1546V18 − only the lower nibble (D
CY7C1548V18 − only the lower byte (D
CY7C1546V18 − only the lower nibble (D
CY7C1548V18 − only the lower byte (D
During the data portion of a write sequence :
CY7C1546V18 − only the upper nibble (D
CY7C1548V18 − only the upper byte (D
CY7C1546V18 − only the upper nibble (D
CY7C1548V18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
table. NWS
[3, 9]
[17:0]
[17:0]
[7:0]
[7:0]
) are written into the device.
) are written into the device.
0
) are written into the device,
) are written into the device,
, NWS
[8:0]
[8:0]
[17:9]
[17:9]
[3:0]
[3:0]
1
[7:4]
[7:4]
, BWS
) is written into the device, D
) is written into the device, D
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
0
, BWS
[3, 9]
1
, BWS
2
[8:0]
[8:0]
, and BWS
) is written into the device.
) is written into the device.
3
is altered on different portions of a write
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
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