CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Overview
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the input clocks (K and K).
All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, NWS
pass through input registers controlled by the rising edge of the
input clock (K\K).
CY7C1548V18 is described in the following sections. The same
basic descriptions apply to CY7C1546V18, CY7C1557V18, and
CY7C1550V18.
Read Operations
The CY7C1548V18 is organized internally as two arrays of 4M x
18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). Following the next two K clock rising edges, drive the corre-
sponding 18-bit word of data from this address location onto the
Q
quent rising edge of K, drive the next 18-bit data word onto the
Q
of the input clock (K and K). To maintain the internal logic, each
read access is allowed to complete. Read accesses are initiated
on every rising edge of the positive input clock (K).
When read access is deselected, the CY7C1548V18 completes
the pending read transactions. Synchronous internal circuitry
automatically tri-states the outputs following the next rising edge
of the positive input clock (K). This enables a seamless transition
between devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the Write
Address register. On the following K clock rise, the data
presented to D
Data register, provided BWS
subsequent rising edge of the Negative Input Clock (K), the infor-
mation presented to D
register, provided BWS
of data is then written into the memory array at the specified
location. Write accesses are initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that 18
bits of data is transferred into the device on every rising edge of
the input clocks (K and K).
When write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Document Number: 001-06550 Rev. *D
[17:0]
[17:0]
. The requested data is valid 0.45 ns from the rising edge
using K as the output timing reference. On the subse-
[17:0]
is latched and stored into the 18-bit Write
[1:0]
[17:0]
are both asserted active. The 36 bits
[1:0]
is also stored into the Write Data
[x:0]
[x:0]
are both asserted active. On the
) pass through output registers
) pass through input registers
[0:X]
, BWS
[0:X]
) inputs
Byte Write Operations
Byte write operations are supported by the CY7C1548V18. A
write operation is initiated as described in the
section. The bytes that are written are determined by BWS
BWS
data presented is latched and written into the device by asserting
the appropriate Byte Write Select input during the data portion of
a write. Deasserting the Byte Write Select input during the data
portion of a write enables the data stored in the device for that
byte to remain unaltered. This feature is used to simplify read,
modify, and write operations to a byte write operation.
Double Date Rate Operation
The CY7C1548V18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1548V18 requires two No
Operation (NOP) cycles when transitioning from a read to a write
cycle. At higher frequencies, some applications require a third
NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted Write.
If a read is performed on the same address where a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals are common between banks
as appropriate.
Programmable Impedance
An external resistor, RQ, is connected between the ZQ pin on the
SRAM and V
impedance. The value of RQ is 5x the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to
guarantee impedance matching with a tolerance of ±15% is
between 175Ω and 350Ω
impedance is adjusted every 1024 cycles upon power up to
account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
1
, that are sampled with each set of 18-bit data words. The
SS
to enable the SRAM to adjust its output driver
“Switching Characteristics”
,
with V
DDQ
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
= 1.5V. The output
Write Operations
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