CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 12

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent device clocking. TDI and TMS are internally pulled up
and are unconnected. They are alternately connected to V
through a pull up resistor. TDO is left unconnected. Upon power
up, the device comes up in a reset state that does not interfere
with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. Leave this pin uncon-
nected if the TAP is not used. The pin is pulled up internally,
resulting in a logic HIGH level.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers
and is connected to the input of any of the registers. The register
between TDI and TDO is selected by the instruction that is
loaded into the TAP instruction register. For information about
loading the Instruction register, see
Diagram”
nected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSb) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The active state of the output depends on the current
state of the TAP state machine (see
page 17). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSb) of any register.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of the
SRAM and is performed while the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins
enabling data scanning into and out of the SRAM test circuitry.
Only one register is selected at a time through the Instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Document Number: 001-06550 Rev. *D
on page 14. TDI is internally pulled up and is uncon-
“Instruction Codes”
“TAP Controller State
DD
) for five rising
SS
) to
DD
on
Instruction Register
Three-bit instructions is serially loaded into the Instruction
register. This register placed between the TDI and TDO pins is
loaded as shown in
Upon power up, the Instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The Bypass
register is a single-bit register that is placed between TDI and
TDO pins. This enables data shifting through the SRAM with
minimal delay. The Bypass register is set LOW (V
BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the Scan register to reserve pins for higher density
devices.
The Boundary Scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state. It is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
“Boundary Scan Order”
that are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSb of the register is connected to TDI
and the LSb is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the Instruction register. The IDCODE is hardwired into
the SRAM and is shifted out, when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other infor-
mation described in
page 17.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in
Codes”
RESERVED and are not used. The other five instructions are
described in this section.
Instructions are loaded into the TAP controller during the Shift-IR
state when the Instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
Instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
Performing a TAP
on page 17. Three of these instructions are listed as
“TAP Controller Block Diagram”
“Identification Register Definitions”
on page 18 shows the order of the bits
Reset.
CY7C1546V18
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CY7C1550V18
Page 12 of 27
SS
on page 15.
“Instruction
) when the
on
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