CY7C1550V18-375BZC Cypress Semiconductor Corp, CY7C1550V18-375BZC Datasheet - Page 19

• Manufacturer Part Number: CY7C1550V18-375BZC
• Description: IC SRAM 72MBIT 375MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1550V18-375BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (2M x 36)
• Speed: 375MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Power Up Sequence in DDR-II+ SRAM
DDR-II+ SRAMs is powered up and initialized in a pre-defined
manner to prevent undefined operations. During power up, when
the DOFF is tied HIGH, the DLL is locked after 2048 cycles of
stable clock.
Power Up Sequence
■
■
Power Up Waveforms
Document Number: 001-06550 Rev. *D
Apply power with DOFF tied HIGH (All other inputs are HIGH
or LOW)
❐
❐
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
Apply V
Apply V
V DD /V DDQ
DOFF
DD
DDQ
before V
before V
K
K
DDQ
REF
or at the same time as V
Clock Start (Clock Starts after V DD /V DDQ is Stable)
Unstable Clock
V DD /V DDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to V DDQ )
Figure 3. Power Up Waveforms
REF
> 2048 Stable Clock
DLL Constraints
■
■
■
DLL uses K clock as its synchronizing input. The input has low
phase jitter that is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL locks onto an incorrect frequency. This causes unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
KC Var
Start Normal
Operation
CY7C1546V18
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