PSD813F1A-90JI STMicroelectronics, PSD813F1A-90JI Datasheet - Page 60

• Manufacturer Part Number: PSD813F1A-90JI
• Description: IC FLASH 1MBIT 90NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90JI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1976-5

PSD813F1A
Enable Out
The Enable Out register can be read by the micro-
controller. It contains the output enable values for
a given port. A ‘1’ indicates the driver is in output
mode. A ‘0’ indicates the driver is in tri-state and
the pin is in input mode.
Ports A and B – Functionality and Structure
Ports A and B have similar functionality and struc-
ture, as shown in Figure 29. The two ports can be
configured to perform one or more of the following
functions:
■
■
Figure 29. Port A and Port B Structure
60/111
MCU I/O Mode
CPLD Output – Macrocells McellAB7-
McellAB0 can be connected to Port A or Port
B. McellBC7-McellBC0 can be connected to
Port B or Port C.
ALE
ADDRESS
MACROCELL OUTPUTS
WR
WR
WR
ENABLE PRODUCT TERM ( .OE )
CONTROL REG.
CPLD-INPUT
DATA OUT
READ MUX
DIR REG.
G
D
D
D
D
REG.
P
D
B
Q
Q
Q
Q
A [ 7:0 ] OR A [ 15:8 ]
ADDRESS
■
■
■
■
■
■
■
DATA OUT
DATA IN
CPLD Input – Via the Input Macrocells (IMC).
Latched Address output – Provide latched
address output as per
Address In – Additional high address inputs
using the Input Macrocells (IMC).
Open Drain/Slew Rate – pins PA3-PA0 and
PB3-PB0 can be configured to fast slew rate,
pins PA7-PA4 and PB7-PB4 can be
configured to Open Drain Mode.
Data Port – Port A to D7-D0 for 8 bit non-
multiplexed bus
Multiplexed Address/Data port for certain
types of MCU bus interfaces.
Peripheral Mode – Port A only
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
INPUT
Table 21., page
A OR B PIN
PORT
55.
AI02887