PSD813F1A-12JI STMicroelectronics, PSD813F1A-12JI Datasheet
PSD813F1A-12JI
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PSD813F1A-12JI Summary of contents
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... Internal page register that can be used to expand the microcontroller address space by a factor of 256. ■ PROGRAMMABLE POWER MANAGEMENT October 2008 This is information on a product still in production but not recommended for new designs. PSD813F1A for 8-bit MCUs Figure 1. Packages PQFP52 (M) PLCC52 (J) TQFQ64 (U) ■ ...
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... PSD813F1A TABLE OF CONTENTS Features Summary SUMMARY DESCRIPTION In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 In-Application Programming (IAP Simultaneous read and write to Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSDsoft Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSD ARCHITECTURAL OVERVIEW ...
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... Memory Select Configuration for MCUs with Separate Program and Data Spaces . . . . . . . . 31 Separate Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PLD’ The Turbo Bit in PSD DECODE PLD (DPLD COMPLEX PLD (CPLD Output Macrocell (OMC Product Term Allocator Loading and Reading the Output Macrocells (OMC The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PSD813F1A 3/111 ...
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... PSD813F1A The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Macrocells (IMC MCU BUS INTERFACE PSD Interface to a Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PSD Interface to a Non-Multiplexed 8-Bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Data Byte Enable Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O PORTS General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Port Operating Modes ...
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... I/O Pin, Register and PLD Status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 71 Standard JTAG Signals JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Security, Flash memory and EEPROM Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 INITIAL DELIVERY STATE AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 REVISION HISTORY 110 PSD813F1A 5/111 ...
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... PSD813F1A SUMMARY DESCRIPTION The PSD family of Programmable Microcontroller (MCU) Peripherals brings In-System Programma- bility (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. ...
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... Figure 2. PQFP52 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 PSD813F1A 39 AD15 38 AD14 37 AD13 36 AD12 35 AD11 34 AD10 33 AD9 32 AD8 AD7 29 AD6 28 AD5 27 AD4 AI02858 7/111 ...
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... PSD813F1A Figure 3. PLCC52 Connections 8 PD2 9 PD1 10 PD0 11 PC7 12 PC6 13 PC5 14 PC4 GND 17 PC3 18 PC2 19 PC1 20 PC0 8/111 AD15 46 AD14 45 44 AD13 AD12 43 AD11 42 41 AD10 AD9 40 AD8 AD7 37 AD6 36 AD5 35 AD4 34 AI02857 ...
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... Figure 4. TQFP64 Connections PD2 1 PD1 2 PD0 3 PC7 4 PC6 5 PC5 6 PC4 GND 9 GND 10 PC3 11 PC2 12 PC1 13 PC0 PSD813F1A 48 CNTL0 47 AD15 46 AD14 45 AD13 44 AD12 43 AD11 42 AD10 41 AD9 40 AD8 AD7 36 AD6 35 AD5 34 AD4 33 AD3 AI09644 9/111 ...
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... PSD813F1A PIN DESCRIPTION Table 1. Pin Description (for the PLCC52 package) Pin Name Pin Type This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port ...
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... MCU I/O – write to or read from a standard output or input port. 2. CPLD macrocell (McellBC4) output. PC4 14 I/O 3. Input to the PLDs. 4. TERR output This pin can be configured as a CMOS or Open Drain output. Description 2 for the JTAG Interface. 2 for the JTAG Interface. 2 for the JTAG Serial Interface. 2 for the JTAG Interface. PSD813F1A (1) 11/111 ...
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... PSD813F1A Pin Name Pin Type PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O – write to or read from a standard output or input port. 2. CPLD macrocell (McellBC5) output. PC5 13 I/O 3. Input to the PLDs. 4. TDI input This pin can be configured as a CMOS or Open Drain output. ...
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... Figure 5. Block Diagram PSD813F1A AI02861G 13/111 ...
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... PSD813F1A PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 5 shows the architecture of the PSD device. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configu- rable. Memory The PSD contains the following memories: ■ ...
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... PC0 PC1 PC3 PC4 PC5 PC6 JTAG Programming Device Programmer Yes Yes Yes Yes Yes Yes Yes Yes No Yes PSD813F1A section entitled for more details. JTAG Signal TMS TCK TSTAT TERR TDI TDO In-System Parallel Programming Yes Yes No No Yes POWER ...
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... PSD813F1A DEVELOPMENT SYSTEM The PSD is supported by PSDsoft Express a Win- dows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Definition Lan- guage (HDL) equations (unless desired) to define PSD pin functions and memory map information. ...
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... Enables JTAG Port B0 Power Management Register 0 B4 Power Management Register 2 E0 Page Register Places PSD memory areas in Program and/or Data E2 space on an individual basis. PSD813F1A provides brief descriptions of the registers (2) Port B Port B (3:0) Port B (7:4) Address a11-a8 N/A Address a11-a8 Address a15-a12 ...
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... Flash or EEPROM memory blocks are being written to, or when the Flash memory block is being erased. The output will be a ‘1’ (Ready) when no write or erase operation is in progress. Table 7. Memory Blocks Device Main Flash PSD813F1A 128KB decode EEPROM SRAM 32KB 2KB ...
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... The status test is very similar to that 20. used for Flash memory (READ operation or Ready/Busy). Optionally, the EEPROM memory may be put into a Software Data Protect (SDP) mode where it requires instructions, rather than operations, to alter its contents. SDP mode makes writing to EEPROM much like writing to Flash memory. PSD813F1A 19/111 ...
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... PSD813F1A Table 8. Instructions EEPROM Flash Sector Instruction Sector Select Select (FSi) (EESi) Read Flash 0 3,5 Identifier Read OTP 1 4 row Read Sector Protection 0 3,5 Status Program Flash Byte Erase one 0 5 Flash Sector Erase the 0 5 Whole Flash Suspend 0 5 Sector Erase ...
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... Any write cycle initiation is locked when V is below V CC PSD813F1A are detailed in Table EE- Ta- ...
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... PSD813F1A READ Under typical conditions, the microcontroller may read the Flash or EEPROM memory using READ operations just as it would a ROM or RAM device. Alternately, the microcontroller may use READ op- erations to obtain status information about a Pro- gram or Erase operation in progress. Lastly, the microcontroller may use instructions to read spe- cial data from these memories ...
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... The Erase timer bit is set to ‘0’ after a Sector Erase instruction for a time period of 100µs + 20% unless an additional Sector Erase instruc- tion is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to ‘1.’ PSD813F1A 23/111 ...
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... PSD813F1A Writing to the EEPROM Data may be written a byte at a time to the EE- PROM using simple write operations, much like writing to an SRAM. Unlike SRAM though, the completion of each byte write must be checked be- fore the next byte is written. To speed up this pro- cess, the PSD offers a Page write feature to allow writing of several bytes before checking status ...
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... Set WRITE AAh to Address 555h WRITE 55h to Address AAAh Page Write Instruction WRITE A0h to Address 555h WRITE Data to be Written in any Address Write in Memory PSD813F1A SDP not Set WRITE is enabled Write Data + SDP Set after tWC (Write Cycle Time) ai09219 25/111 ...
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... PSD813F1A Figure 8. Software Data Protection Disable Flowchart 26/111 WRITE AAh to Address 555h WRITE 55h to Address AAAh WRITE 80h to Address 555h Page Write Instruction WRITE AAh to Address 555h WRITE 55h to Address AAAh WRITE 20h to Address 555h Unprotected State after tWC (Write Cycle time) ...
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... DQ7 and DQ5. PSDsoft Express will generate ANSI C code func- tions which implement these Data Polling algo- rithms. Figure 9. Data Polling Flowchart READ DQ5 & DQ7 at VALID ADDRESS NO READ DQ7 PSD813F1A 9 still applies. However, START DQ7 YES = DATA NO DQ5 ...
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... PSD813F1A Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase in- struction is in progress or has completed. Figure 10 shows the Data Toggle algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the byte to be programmed in Flash to check status ...
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... If an Erase Suspend instruction was previously ex- ecuted, the erase operation may be resumed by this instruction. The Erase Resume instruction PROGRAM- consists of writing 030h to any address while an 27. appropriate Chip Select (FSi) is true. (See 8., page PSD813F1A 20). This allows reading of data from 20.) Ta- Table 29/111 ...
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... PSD813F1A FLASH AND EEPROM MEMORY SPECIFIC FEATURES Flash Memory and EEPROM Sector Protect Each Flash and EEPROM sector can be separate- ly protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase opera- tions. This mode can be activated through the JTAG Port or a Device Programmer ...
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... Flash access EEPROM Flash memory memory PSEN access access access Flash EEPROM Flash memory memory PSD813F1A Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary EEPROM Memory Level 3 Flash Memory Bit 2 Bit 1 FL_Code EE_Code SRAM_Code 0 = PSEN 0 = PSEN can’t can’t access ...
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... PSD813F1A Separate Space Modes Code memory space is separated from data mem- ory space. For example, the PSEN signal is used to access the program code from the Flash Mem- ory, while the RD signal is used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch ...
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... Page Register. The Page Regis- ter can be accessed at address location CSIOP + E0h. RESET PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 PGR7 PAGE REGISTER PSD813F1A shows the Page Register. The eight flip INTERNAL SELECTS AND LOGIC Flash DPLD AND Flash CPLD PLD AI09224 33/111 ...
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... PSD813F1A PLD’S The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using the PSDabel tool in PSDsoft Express, the logic is programmed into the device and available upon power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD) ...
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... Figure 15. PLD Diagram PORTS I/O BUS INPUT PLD PSD813F1A 35/111 ...
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... PSD813F1A DECODE PLD (DPLD) The DPLD, shown in Figure 16, is used for decod- ing the address for internal and external compo- nents. The DPLD can be used to generate the following decode signals: ■ 8 sector selects for the main Flash memory (three product terms each) ■ ...
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... MCU LOAD MACROCELL OUT TO MCU D/T Q CPLD D/T/JK FF COMB. OUTPUT SELECT /REG SELECT MACROCELL CK TO I/O PORT CL ALLOC. PSD813F1A TO OTHER I/O PORTS I/O PORTS LATCHED ADDRESS OUT I/O PIN DATA D Q MUX WR CPLD OUTPUT SELECT PDR INPUT Q D DIR REG. WR INPUT MACROCELLS ...
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... PSD813F1A Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are con- nected to Ports A and B pins and are named as McellAB0-McellAB7. The other eight macrocells are connected to Ports B and C pins and are named as McellBC0-McellBC7 McellAB out- put is not assigned to a specific pin in PSDabel, the Macrocell Allocator will assign it to either Port ...
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... PLD output in PSDsoft Express. If the OMC output is declared as an internal node and not as a Port pin output in the PSDabel file, then the Port pin can be used for other I/O func- tions. The internal node feedback can be routed as an input to the AND array. PSD813F1A 39/111 ...
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... PSD813F1A Figure 18. CPLD Output Macrocell 40/111 ARRAY AND BUS INPUT PLD ...
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... The Slave can also write to the Port A IMCs and the Master can then read the IMCs directly. Note that the “Slave-Read” and “Slave-wr” signals are product terms that are derived from the Slave MCU inputs RD, WR, and Slave_CS. PSD813F1A 41/111 ...
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... PSD813F1A Figure 19. Input Macrocell 42/111 ARRAY AND BUS INPUT PLD ...
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... Figure 20. Handshaking Communication Using Input Macrocells PSD813F1A 43/111 ...
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... PSD813F1A MCU BUS INTERFACE The “no-glue logic” PSD MCU Bus Interface block can be directly connected to most popular MCUs and their control signals. Table 15. MCUs and their Control Signals Data Bus MCU Width 8031 8 80C51XA 8 80C251 8 80C251 8 80198 8 68HC11 8 68HC912 8 Z80 ...
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... B. The PSD drives the ADIO data bus only when one of its internal resources is accessed and Read Strobe (RD, CNTL1) is active. Should the system address bus exceed sixteen bits, Ports may be used as additional address inputs. PSD 15:8 ] PSD813F1A PORT A ( OPTIONAL ) ADIO PORT ...
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... PSD813F1A PSD Interface to a Non-Multiplexed 8-Bit Bus Figure 22 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a PSD. The address bus is connected to the ADIO Port, and the data bus is connected to Port Figure 22. An Example of a Typical 8-bit Non-Multiplexed Bus Interface ...
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... A15 P2 PSEN PSEN 30 ALE ALE/P 11 TXD 10 RXD RESET PSD813F1A to 26 show examples of the basic con- 48. There is only one READ input Figure 24., page 49. The RD signal is shows the bus interface for the 80C31, AD7-AD0 AD [ 7:0 ] PSD 30 29 ADIO0 PA0 31 28 ADIO1 PA1 27 32 ...
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... PSD813F1A 80C251 The Intel 80C251 MCU features a user-configu- rable bus interface with four possible bus configu- rations, as shown in Table 18., page The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In Non-Page Mode, the data is multiplexed with the lower ad- dress byte, and ALE is active in every bus cycle ...
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... AD15 31 P2.7 33 ALE ALE 32 RD PSEN PSEN RD/A16 RESET Connecting to PSD Pins CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2 PSD813F1A PSD A0 30 ADIO0 A1 31 ADIO1 A2 32 ADIO2 33 A3 ADIO3 A4 34 ADIO4 A5 35 ADIO5 36 A6 ADIO6 A7 37 ADIO7 AD8 ...
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... PSD813F1A 80C51XA The Philips 80C51XA microcontroller family sup- ports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multi- plexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11- A4) are multiplexed with data bits (D7-D0). ...
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... PC4 14 AD5 PC5 15 AD6 PC6 16 AD7 PC7 20 PD0 21 PD1 22 PD2 23 PD3 24 PD4 25 PD5 3 MODA RESET PSD813F1A AD7-AD0 AD7-AD0 PSD 30 29 ADIO0 PA0 31 28 ADIO1 PA1 27 32 PA2 ADIO2 33 25 ADIO3 PA3 34 24 AD104 PA4 35 23 AD105 PA5 36 22 PA6 ADIO6 37 21 ...
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... PSD813F1A I/O PORTS There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Ex- press Configuration or by the MCU writing to on- chip registers in the CSIOP address space ...
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... Figure 27. General I/O Port Architecture DATA OUT REG ADDRESS D ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT DATA OUT Q ADDRESS Q DATA PSD813F1A PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL AI02885 53/111 ...
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... PSD813F1A MCU I/O Mode In the MCU I/O Mode, the microcontroller uses the PSD ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the microcontroller address space. The addresses of the ports are listed in 6., page 17 ...
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... N/A N/A N/A N/A N/A N/A JTAG Configuration N/A N/A Port A (PA7-PA4) Port B (PB3-PB0) Address a7-a4 Address A11-A8 N/A Address A11-A8 Address A7-A4 Address A3-A0 N/A Address A3-A0 PSD813F1A VM Register Register JTAG Enable Setting Setting N/A N N/A N/A ) N/A N/A 2 N/A ...
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... PSD813F1A Address In Mode For microcontrollers that have more than 16 ad- dress lines, the higher addresses can be connect Port and D. The address input can be latched in the Input Macrocell by the address strobe (ALE/AS). Any input that is included in the DPLD equations for the PLD’s Flash, EEPROM, or SRAM is considered address input ...
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... Address Out Mode. The default mode is MCU I/O. Only Ports A and B have an associated Control Register. Ta- Table 22. Port Configuration Registers (PCR) Register Name Control Direction Drive Select Note: 1. See PSD813F1A 22 is 00h. Port MCU Access A,B WRITE/READ A,B,C,D WRITE/READ 1 A,B,C,D WRITE/READ Table 26 ...
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... PSD813F1A Direction Register The Direction Register, in conjunction with the out- put enable (except for Port D), controls the direc- tion of data flow in the I/O Ports. Any bit set to ‘1’ in the Direction Register will cause the corre- sponding pin output, and any bit set to ‘0’ ...
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... WRITE – loading macrocell flip-flop WRITE/READ – prevents loading into a given A,B,C macrocell A,B,C READ – outputs of the Input Macrocells A,B,C READ – the output enable control of the port driver PSD813F1A PLD’S, page to the section entitled for a detailed description. MCU Access 59/111 34 ...
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... PSD813F1A Enable Out The Enable Out register can be read by the micro- controller. It contains the output enable values for a given port. A ‘1’ indicates the driver is in output mode. A ‘0’ indicates the driver is in tri-state and the pin is in input mode. ...
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... Pin PC7 may be configured as the DBE input in certain MCU interfaces. DATA OUT REG. DATA OUT SPECIAL FUNCTION READ MUX P D DATA IN B DIR REG PSD813F1A PORT C PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL 1 SPECIAL FUNCTION CONFIGURATION BIT 71, for AI02888B 61/111 ...
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... PSD813F1A Port D – Functionality and Structure Port D has three I/O pins. See Figure ure 32., page 63. This port does not support Ad- dress Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions: ■ MCU I/O Mode ■ ...
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... The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 32.) ENABLE (.OE) PT0 POLARITY BIT ENABLE (.OE) PT1 POLARITY BIT ENABLE (.OE) PT2 POLARITY BIT PSD813F1A DIRECTION REGISTER PD0 PIN ECS0 DIRECTION REGISTER PD1 PIN ECS1 DIRECTION REGISTER PD2 PIN ECS2 AI02890 63/111 ...
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... PSD813F1A POWER MANAGEMENT The PSD offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: – All memory types in a PSD (Flash, EEPROM, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology ...
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... DISABLE BUS DETECTION INTERFACE CLR PD APD COUNTER EDGE PD DETECT Memory Access Recovery Time Access Time to Normal Access No Access t LVDV PSD813F1A 28 Port Function Pin Level No Change No Change Undefined Tri-State Tri-State EEPROM SELECT FLASH SELECT PLD SRAM SELECT POWER DOWN ( PDN ) SELECT AI02891 ...
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... PSD813F1A For Users of the HC11 (or compatible) The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compati- ble) in your design, and you wish to use the Pow- er-down mode, you must not connect the E clock to CLKIN (PD1). You should instead connect an independent clock signal to the CLKIN input (PD1) ...
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... CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN (PD1) Powers-up the PLD when Turbo bit is 0. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. Not used, and should be set to zero. PSD813F1A 67/111 ...
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... PSD813F1A Input Control Signals The PSD provides the option to turn off the input control signals (CNTL0, CNTL1, CNTL2, ALE, and DBE) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND array. Table 32. APD Counter Operation APD Enable Bit ...
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... Once the PLD is active, the state of the outputs are determined by the PSDabel equa- tions. EEH- is below LKO t OPR PSD813F1A NLNH and 68 for values). The same t 35 shows the timing of the shows the I/O pin, register and ramps up to operat- ...
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... PSD813F1A Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Data Port Tri-stated Peripheral I/O Tri-stated Register PMMR0 and PMMR2 Cleared to ‘0’ ...
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... ST. ST’s PSDsoft Express software tool and FlashLink JTAG programming cable im- plement these JTAG-ISC commands. This docu- ment is needed only as a reference for designers who use a FlashLink to program their PSD. PSD813F1A Table for bit definition. */ 71/111 ...
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... PSD813F1A JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed programming and erase functions by indicating status on PSD pins instead of having to scan the status out seri- ally using the standard JTAG channel ...
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... The AC power component gives the PLD, EEPROM and SRAM mA/MHz specification. Figures a function of the number of Product Terms (PT) used. ■ In the PLD timing parameters, add the required delay when Turbo bit is ‘0 PSD813F1A 36 and 37 show the PLD mA/MHz as PT 100 AI02894 PT 100 AI03100 73/111 ...
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... PSD813F1A Table 36. Example of PSD Typical Power Calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access % SRAM access % I/O access Operational Modes % Normal % Power-down Mode Number of product terms used (from fitter report total product terms ...
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... Ipwrdown x %pwrdown + %normal Ipwrdown x %pwrdown + % normal x (%flash x 2.5mA/MHz x Freq ALE + %SRAM x 1.5mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50µA x 0.90 + 0.1 x (0.8 x 2.5mA/MHz x 4MHz + 0.15 x 1.5mA/MHz x 4MHz + 24mA) = 45µ 0.9 + 24) = 45µA + 0.1 x 32.9 = 45µA + 3.29mA = 3.34mA PSD813F1A (ac (dc OUT 75/111 ...
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... PSD813F1A MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 38 ...
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... Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. Parameter Parameter Table 42. AC Signal Behavior Symbols for PLD Timings Note: Example: t Parameter PSD813F1A Min. Max. Unit 4.5 5.5 V –40 85 ° °C Min. Max. Unit 3.0 3 ...
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... PSD813F1A Table 44. Capacitance Symbol Parameter C Input Capacitance (for input pins) IN Output Capacitance (for input/ C OUT output pins) C Capacitance (for CNTL2/V VPP Note: 1. Sampled only, not 100% tested. 2. Typical values are for T = 25°C and nominal supply voltages. A Figure 38. AC Measurement I/O Waveform 3 ...
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... Read only 0MHz f = 0MHz is valid at or below 0.2V –0.1. V IL1 CC IH1 for the PLD current calculation. Conditions 3.0V < V < 3.6V CC 3.0V < V < 3. (Note ) 1 (Note ) PSD813F1A Min. Typ. Max. 0. 0.2V –0.1 –0.5 CC 0.3 2.5 4.2 0.01 0.1 0.25 0.45 4.4 4 ...
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... PSD813F1A Symbol Parameter V Reset Pin Hysteresis HYS V (min) for Flash Erase and CC V LKO Program V Output Low Voltage OL V Output High Voltage OH Standby Supply Current I SB for Power-down Mode I Input Leakage Current LI I Output Leakage Current LO ZPLD Only Operating I (DC) CC Supply ...
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... Preset Pulse Width t CPLD Array Delay ARD Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. ZPSD versions only -90 -12 Conditions Min Max Min Max Min Max Any 16 macrocell PSD813F1A -15 Fast Turbo Slew PT 2 Off rate Aloc ...
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... PSD813F1A Table 48. CPLD Combinatorial Timing (3V devices) Symbol Parameter CPLD Input Pin/Feedback t to CPLD Combinatorial PD Output CPLD Input to CPLD Output t EA Enable CPLD Input to CPLD Output t ER Disable CPLD Register Clear or t ARP Preset Delay CPLD Register Clear or t ARPW Preset Pulse Width ...
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... Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount. 2. CLKIN (PD1 CLCL CH CL -90 -12 Min Max Min Max 30 26 43.4 +t –10 41. PSD813F1A -15 Fast Turbo PT Off Min Max Aloc 23.8 31.25 33 Slew Unit 1 rate MHz MHz MHz – 83/111 ...
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... PSD813F1A Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time CH t Clock Low Time CL t Clock to Output Delay ...
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... Minimum t 1/f MINA Clock Period Note: 1. ZPSD versions only. -90 -12 Min Max Min Max 26 23.25 COA 2 35.7 +t –10) 30.30 COA 1 41 35.71 CLA CNTA PSD813F1A -15 Turbo PT 1 Aloc Off Min Max 20.4 25.64 33 Slew Unit Rate MHz MHz MHz – 85/111 ...
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... PSD813F1A Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f Internal Feedback MAXA (f ) CNTA Maximum Frequency Pipelined Data t Input Setup Time SA t Input Hold Time HA t Clock High Time CHA t Clock Low Time CLA ...
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... Min Max Min Max Min Max (Note ) (Note ) (Note ) (Note ) 1 46 (Note ) -15 Conditions Min Max 1 0 (Note ) 1 25 (Note ) 1 13 (Note ) 1 13 (Note ) 1 62 (Note ) PSD813F1A t INO -15 Turbo PT 2 Aloc Off and t . AVLX LXAX -20 Turbo PT 2 Aloc Off Min Max and t . AVLX LXAX 87/111 Unit ...
Page 88
... PSD813F1A Figure 47. READ Timing ALE / MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS AVPV Note and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. AVLX LXAX 88/111 1 t AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV ...
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... RD timing has the same timing as DS, LDS, and UDS signals Turbo Off mode, add 10ns to t -90 Conditions Min Max Min Max Min Max (Note ) 3 8 (Note ) 3,6 (Notes ) 5 (Note ) 2 (Note ) 1 0 (Note ) 1 32 (Note ) 1 (Note ) (Note ) . AVQV PSD813F1A -12 -15 Turbo Off 120 150 + 10 100 135 150 Unit ns ...
Page 90
... PSD813F1A Table 56. READ Timing (3V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid to Data Valid AVQV t CS Valid to Data Valid SLQV RD to Data Valid 8-Bit Bus t RLQV RD or PSEN to Data Valid 8-Bit Bus, ...
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... BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t AVPV ADDRESS OUT PSD813F1A DATA VALID DATA VALID t DVWH t WHDX t WHAX t EHEL t ELTL t WLMV t WHPV STANDARD MCU I/O OUT AI02896 91/111 ...
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... PSD813F1A Table 57. WRITE, Erase and Program Timing (5V devices) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX Address Valid to Leading t AVWL Edge Valid to Leading Edge of WR SLWL t WR Data Setup Time DVWH t WR Data Hold Time ...
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... Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid t Conditions (Note (Note (Notes (Note (Note (Note (Note (Note (Note (Note (Notes (Note (Notes Parameter (pre-programmed) 2 time units before the data byte, DQ0-DQ7, is valid for reading. Q7VQV PSD813F1A -15 -20 Min Max Min 1 ...
Page 94
... PSD813F1A Table 60. Flash Program, WRITE and Erase Times (3V devices) Symbol Flash Program 1 Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles (per Sector) t Sector Erase Time-Out WHWLO ...
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... DATA ON PORT A -90 Conditions Min Max Min Max Min Max 3 40 (Note ) 35 1,4 32 (Notes ) (Note ) 1 25 (Note ) Conditions Min 3 (Note ) 1,4 (Notes ) (Note ) 1 (Note ) PSD813F1A DATA VALID t QXRH (PA) t RHQZ (PA) t DVQV (PA) AI02897 -12 -15 Turbo Off -15 -20 Turbo Off Max Min Max ...
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... PSD813F1A Figure 50. Peripheral I/O WRITE Timing ALE/ BUS WR Table 65. Port A Peripheral Data Mode WRITE Timing (5V devices) Symbol Parameter Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV– Invalid to Port A Tri-state WHQZ–PA Note has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). ...
Page 97
... NLNH–PO t RESET High to Operational Device OPR Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles 10ms for devices manufactured before the rev.A. NLNH-PO t OPR Conditions 1 Conditions 1 2 PSD813F1A t NLNH t NLNH-A t OPR Warm Reset AI02866b Min Max Unit 150 120 ...
Page 98
... PSD813F1A Figure 52. ISC Timing t TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 69. ISC Timing (5V devices) Symbol Parameter Clock (TCK, PC1) Frequency (except for t ISCCF PLD) Clock (TCK, PC1) High Time (except for t ISCCH PLD) Clock (TCK, PC1) Low Time (except for t ISCCL ...
Page 99
... Conditions Min Max Min Max Min Max 90 Using CLKIN (PD1) -15 Conditions Min Max 150 Using CLKIN (PD1) PSD813F1A -20 Unit Min Max 9 MHz MHz 240 ns 240 -12 -15 Unit 120 150 ns 1 µs CLCL -20 Unit ...
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... PSD813F1A PACKAGE MECHANICAL In order to meet environmental requirements, ST offers these devices in ECOPACK These packages have a Lead-free second level in- terconnect. The category of second level intercon- nect is marked on the package and on the inner Figure 53. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing QFP-A Note: Drawing is not to scale. ...
Page 101
... PSD813F1A inches Min. Max. 0.093 0.010 0.077 0.083 0.009 0.015 0.004 0.009 0.518 0.522 0.392 0.396 – – 0.518 0.522 0.392 0.396 – ...
Page 102
... PSD813F1A Figure 54. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing PLCC-B Note: Drawing is not to scale. Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions Symbol Typ 1. 102/111 E1 E D2/ Min. Max. 4.19 4.57 2.54 2.79 – 0.91 0.33 ...
Page 103
... Figure 55. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline QFP-A Note: Drawing is not to scale PSD813F1A 103/111 ...
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... PSD813F1A Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data Symb. Typ 0.10 A2 1.40 α 3.5° 16.00 D1 14.00 D2 12.00 E 16.00 E1 14.00 E2 12.00 e 0.80 L 0.60 L1 1. 104/111 mm Min. Max. Typ. 1.42 1.54 0.07 0.14 0.004 1.36 1.44 0.055 0.0° ...
Page 105
... Flash Memory 1 = 256 Kbit EEPROM Operating Voltage blank = V = 4.5 to 5.5V CC Speed 70 = 70ns 90 = 90ns 12 = 120ns 15 = 150ns Package J = ECOPACK PLCC52 M = ECOPACK PQFP52 U = ECOPACK TQFP64 Temperature Range blank = 0 to 70°C (commercial –40 to 85°C (industrial) Option T = Tape & Reel Packing PSD8 PSD813F1A – 105/111 ...
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... PSD813F1A For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 106/111 ...
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... Pin Number PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 AD3 PSD813F1A Pin Assignments 27 AD4 28 AD5 29 AD6 30 AD7 AD8 33 AD9 34 AD10 35 AD11 36 AD12 37 AD13 38 AD14 39 ...
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... PSD813F1A APPENDIX B. PLCC52 PIN ASSIGNMENTS Table 78. PLCC52 Connections (Figure 3) Pin Number Pin Assignments 108/111 Pin Number GND PB5 PB4 PB3 PB2 PB1 PB0 PD2 PD1 PD0 PC7 PC6 PC5 PC4 V CC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 ...
Page 109
... PD0 PC7 PC6 PC5 PC4 GND GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND GND PA2 PA1 PA0 AD0 AD1 N/D AD2 PSD813F1A Pin Assignments 33 AD3 34 AD4 35 AD5 36 AD6 37 AD7 AD8 41 AD9 42 AD10 43 AD11 AD12 44 45 AD13 46 AD14 ...
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... Table 75) 04-Aug-04 4.0 Correct connection, assignment (Figure 4; Table 79) Part number changed to PSD813F1A. Added ECOPACK text in cover page and in section Updated datasheet status to “not for new design”. Backup battery feature removed: updated Features Summary, Table 1 (pins PC2 and PC4), Block Diagram figure, Memory section, SRAM section, Port C – ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com PSD813F1A 111/111 ...