psd813f1a-90ut STMicroelectronics, psd813f1a-90ut Datasheet
psd813f1a-90ut
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psd813f1a-90ut Summary of contents
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... Flash In-System Programmable (ISP) Peripherals FEATURES SUMMARY Single Supply Voltage: – 5 V±10% for PSD913F1 – 3.3 V±10% for PSD913F1 1Mbit of Primary Flash Memory (8 uniform sectors) 256Kbit Secondary EEPROM (4 uniform sectors 16Kbit SRAM Over 2,000 Gates of PLD: DPLD 27 Reconfigurable I/O ports ...
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... Preliminary 1.0 The PSD913F1 family of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a Introduction simple and flexible solution for embedded designs. PSD913F1 devices combine many of the peripheral functions found in MCU based applications: • 1 Mbit of Flash memory • ...
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... PSD913F1 1.0 The PSD913F1 family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board. Introduction (Cont.) In-System Programming (ISP) JTAG An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire device (Flash memory, EEPROM, the PLD, and all configuration rapidly programmed while soldered to the circuit board ...
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... Philips 8031 and 8051XA • Zilog Z80 and Z8 Internal 1 Mbit Flash memory. This is the main Flash memory divided into eight equal-sized blocks that can be accessed with user-specified addresses. Internal secondary 256 Kbit EEPROM memory divided into four equal-sized blocks that can be accessed with user-specified addresses ...
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PSD913F1 Figure 1. PSD913F1 Block Diagram 4 Preliminary ...
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... Information 4.0 All PSD913F1 devices provide these base features: 1 Mbit main Flash Memory, JTAG port, GPLD, DPLD, power management, and 27 I/O pins. The PSD913F1 also adds 64 bytes of PSD913F1 OTP memory for any use (product serial number, calibration constants, etc.). Once written, Family the OTP memory can never be altered ...
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... The 256 Kbit EEPROM or Flash is divided into four equally-sized sectors. Each sector is individually selectable. The 16 Kbit SRAM is intended for use as a scratchpad memory extension to the microcontroller SRAM external battery is connected to the PSD913F1’s Vstby pin, data will be retained in the event of a power failure. ...
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Preliminary PSD913F1 5.4 I/O Ports Architectural The PSD913F1 has 27 I/O pins divided among four ports (Port and D). Each I/O pin can be individually configured for different functions. Ports and D can be ...
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... EEPROM or SRAM. The EEPROM can be programmed the same way by executing out of the main Flash memory. The PLD logic or other PSD913F1 configuration can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD913F1. ...
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... Development environment. The designer does not need to enter Hardware Definition Language (HDL) System equations (unless desired) to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below. PSDsoft is available from our web site (www.psdst.com) or other distribution channels. ...
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PSD913F1 7.0 The following table describes the pin names and pin functions of the PSD913F1. Pins that have multiple names and/or functions are defined using PSDsoft. Table 5. PSD913F1 Pin Name Pin Descriptions ADIO0-7 ADIO8-15 CNTL0 CNTL1 10 Pin* Type ...
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Preliminary Table 5. Pin Name Pin* Type PSD913F1 Pin CNTL2 Descriptions (cont.) Reset PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 (PLCC This pin can be used to ...
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PSD913F1 Table 5. Pin Name Pin* Type PSD913F1 Pin PC2 Descriptions (cont.) PC3 PC4 PC5 PC6 12 (PLCC) 18 I/O PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O — ...
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... MCU I/O — write to or read from a standard output or input port. 2. Input to the PLDs. 3. General purpose PLD output. 4. CSI — chip select input. When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. 15, 38 Power pins 1,16,26 ...
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... Read only – Flash Sector C0 Protection Read only – PSD Security C2 and EEPROM Sector Protection Power Management B0 Register 0 Power Management B4 Register 2 E0 Page Register Places PSD memory areas in Program and/or E2 Data space on an individual basis. ...
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... Device PSD913F1 9.1.1 Main Flash and Secondary EEPROM The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The EEPROM memory is divided into four sectors of eight Kbytes each. Each sector of either memory can be separately protected from program and erase operations. ...
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... ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event ...
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... The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). An invalid combination or time-out while addressing the EEPROM block will cause the offending byte to be interpreted as a single operation ...
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... The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other memory when these instructions are performed. 5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended. The MCU must operate from some other memory when these instructions are executed ...
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... ID only when it is executing from the EEPROM. 9.1.1.5.3 Read the Main Flash Memory Sector Protection Status The main Flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9). During the read operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select FSi designates the Flash sector whose protection has to be verified ...
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... The 9.1.1.5.4 Read the OTP Row PSD913F1 There are 64 bytes of One-Time-Programmable (OTP) memory that reside in EEPROM. These 64 bytes are in addition to the 32 Kbytes of EEPROM memory. A read of the Functional OTP row is done with an instruction composed of at least 4 operations: 3 specific write Blocks operations and one to 64 read operations (see Table 9). During the read operation(s), (cont ...
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... When the internal cycle is complete, the toggling will stop and the data read on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data ...
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... Instructions from the MCU are used to enable and disable SDP mode (see Table 9). Once enabled, the MCU must write an instruction sequence to EEPROM before writing data (much like writing to Flash memory). SDP mode can be used for both byte and page writes to EEPROM. The device will remain in SDP mode until the MCU issues a valid SDP disable instruction ...
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... PSD913F1 To enable SDP mode at run time, the MCU must write three specific data bytes at three specific memory locations, as shown in Figure 3. Any further writes to EEPROM when SDP Functional is set will require this same sequence, followed by the byte(s) to write. The first SDP enable Blocks sequence can be followed directly by the byte( written ...
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... Programming Flash Memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector basis, programming Flash memory occurs on a byte basis ...
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Preliminary The 9.1.1.7.1 Data Polling PSD913F1 Polling on DQ7 is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 5 shows the Data Polling algorithm. Functional Blocks When the MCU issues a ...
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PSD913F1 The 9.1.1.7.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or PSD913F1 Erase instruction is in progress or has completed. Figure 6 shows the Data Toggle Functional algorithm. Blocks When ...
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... Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. (cont.) During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.7. The Error bit (DQ5) returns a ‘1’ if there has been an Erase Failure (maximum number of erase cycles have been executed) ...
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... Not used. Bit Definitions: Sec<i>_Prot Sec<i>_Prot Security_Bit 9.1.1.9.2 Reset Instruction The Reset instruction resets the internal memory logic state machine in a few milliseconds. Reset is an instruction of either one write operation or three write operations (refer to Table 9). 28 Bit 6 Bit 5 Bit 4 Sec6_Prot Sec5_Prot Sec4_Prot 1 = Flash < ...
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... Preliminary The 9.1.2 SRAM PSD913F1 The SRAM Kbit ( memory. The SRAM is enabled when RS0— the SRAM chip select output from the DPLD— is high. RS0 can contain up to two product terms, Functional allowing flexible memory mapping. Blocks (cont.) The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PC2) ...
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... The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151, 80C251, 80C51XA, and the C500 family, have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD913F1 can reside in either space or both spaces. This is controlled through manip- ulation of the VM register that resides in the PSD’ ...
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... Functional Code memory space is separated from data memory space. For example, the PSEN Blocks signal is used to access the program code from the Flash Memory, while the RD signal is used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires (cont.) the VM register to be set to 0Ch. ...
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... Blocks the Flash Memory, EEPROM, and SRAM chip select equations. (cont.) If memory paging is not needed not all 8 page register bits are needed for memory paging, then these bits may be used in the PLD for general logic. See Application Note. Figure 10 shows the Page Register. The eight flip flops in the register are connected to the internal data bus D0-D7 ...
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... PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O port selects. The GPLD can be used to generate external chip selects, control signals or logic functions. ...
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... PORT B PLD INPUT 8 PORT D PLD INPUT 3 (INPUTS) (24) (8) (16) (3) (1) (3) (1) (1) Preliminary PORT A PORT B PORT D PORT C EES 0 3 EES EEPROM SECTOR SELECTS EES 2 3 EES FS0 FLASH MEMORY SECTOR SELECTS FS7 RS0 2 SRAM SELECT CSIOP I/O DECODER SELECT ...
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... The DPLD can generate the following chip selects: • 8 sector selects for the main Flash memory (three product terms each) • 4 sector selects for the Secondary Flash memory (three product terms each) • 1 internal SRAM select (two product terms) • ...
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PSD913F1 Figure 13. The General Purpose PLD and I/O Port 36 PLD INPUT BUS Preliminary ...
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Preliminary The 9.3 Microcontroller Bus Interface PSD913F1 The “no-glue logic” PSD913F1 Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their Functional bus types and control signals are shown in ...
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PSD913F1 The Figure 14. An Example of a Typical 8-Bit Multiplexed Bus Interface PSD913F1 Functional Blocks (cont.) MICRO- CONTROLLER RESET Figure 15. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface CONTROLLER RESET 7 ...
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... Figure 16 shows the interface to the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. ...
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PSD913F1 The Table 16. 80C251 Configurations PSD913F1 Configuration Functional Blocks (cont.) 9.3.3.3 80C51XA The Philips 80C51XA microcontroller family supports 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are multiplexed ...
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Preliminary Figure 16. Interfacing the PSD913F1 with an 80C31 80C31 31 EA/ RESET RESET 12 INT0 13 INT1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6 P1.5 7 ...
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PSD913F1 Figure 18. Interfacing the PSD913F1 to the 80C251, with Read and PSEN Inputs 80C251SB 2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1 P3.0/RXD 13 P3.1/TXD 14 ...
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Preliminary Figure 20. Interfacing the PSD913F1 with a 68HC11 68HC11 RESET RESET 19 IRQ 18 XIRQ 2 MODB 34 PA0 33 PA1 32 PA2 43 PE0 44 PE1 45 PE2 46 PE3 47 PE4 48 ...
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PSD913F1 The 9.4 I/O Ports PSD913F1 There are four programmable I/O ports: Ports and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus ...
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DATA OUT REG ADDRESS D Q ALE G GPLD OUTPUT READ MUX P D DATA IN B CONTROL REG DIR REG DATA OUT ADDRESS OUTPUT MUX OUTPUT SELECT PLD -INPUT PORT ...
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PSD913F1 The 9.4.2 Port Operating Modes PSD913F1 The I/O Ports have several modes of operation. Some modes can be defined in PSDsoft, some by the microcontroller writing to the Control Registers in CSIOP space, and Functional some by both. The ...
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Preliminary The Table 18. Port Operating Mode Settings PSD913F1 Functional Blocks Mode (cont.) MCU I/O PLD I/O Data Port (Port A) Address Out (Port A,B) Address In (Port A,B,C,D) JTAG ISP * NA = Not Applicable 9.4.2.1 MCU I/O Mode ...
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... For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in Address Out Mode. Note: Do not drive address lines with Address Out Mode to an external memory device intended for the MCU to boot from the external device. The MCU must first boot from PSD memory so the Direction and Control register bits can be set ...
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Preliminary The 9.4.3 Port Configuration Registers (PCRs) PSD913F1 Each port has a set of PCRs used for configuration. The contents of the registers can be Functional accessed by the microcontroller through normal read/write bus cycles at the addresses given in ...
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PSD913F1 The 9.4.3.3 Drive Select Register PSD913F1 The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be ...
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Preliminary The 9.4.4 Port Data Registers PSD913F1 The Port Data Registers, shown in Table 24, are used by the microcontroller to write data to or read data from the ports. Table 24 shows the register name, the ports having each ...
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DATA OUT REG ADDRESS D Q ALE G GPLD OUTPUT READ MUX CONTROL REG DIR REG DATA OUT ADDRESS 15:8 ] ...
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Preliminary The 9.4.6 Port C – Functionality and Structure PSD913F1 Port C can be configured to perform one or more of the following functions (see Figure 23): Functional MCU I/O Mode Blocks PLD Input – Input to the PLDs. (cont.) ...
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DATA OUT REG. DATA OUT SPECIAL FUNCTION READ MUX P D DATA IN B DIR REG PORT C PIN * OUTPUT MUX OUTPUT SELECT PLD-INPUT * SPECIAL FUNCTION CONFIGURATION * JTAG ISP or battery ...
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DATA OUT REG. DATA OUT GPLD OUTPUT READ MUX P D DATA IN B DIR REG PORT D PIN OUTPUT MUX OUTPUT SELECT PLD-INPUT ...
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... PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. ...
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... AS, the PSD913F1 will keep going into Power Down Mode. Ports Pin Level No Change No Change Undefined Three-State Three-State Down Mode PLD Memory Propagation Access Delay Time Normal tpd No Access (Note 1) mode is based only on the Turbo Bit. the PLD Turbo bit is off. ...
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PSD913F1 The Figure 25. APD Logic Block PSD913F1 Functional Blocks APD EN PMMR0 BIT 1=1 (cont.) ALE RESET CSI CLKIN Figure 26. Enable Power Down Flow Chart 58 TRANSITION DETECTION CLR APD COUNTER EDGE DETECT DISABLE FLASH/EEPROM/SRAM RESET Enable APD ...
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Preliminary The Table 27. Power Management Mode Registers (PMMR0, PMMR2)** PSD913F1 PMMR0 Functional Bit 7 Blocks * (cont.) *** Bits and 7 are not used, and should be set to 0, bit 5 should be set to ...
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... Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal selects and enables the internal Flash, EEPROM, SRAM, and I/O for read or write operations involving the PSD913F1. A high on the CSI pin will disable the Flash memory, EEPROM, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O pins remain operational when CSI is high ...
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... PSD913F1 remains in the reset state for an additional tOPR (minimum 120 ns) nanoseconds before the first memory access is allowed. The PSD913F1 Flash or EEPROM memory is reset to the read array mode upon power up. The FSi and EESi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possi- bility of a byte being written on the first edge of a write strobe signal ...
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... Programming In-Circuit using the JTAG Interface The JTAG interface on the PSD913F1 can be enabled on Port C (see Table 30). All memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be programmed through the JTAG interface. A blank part can be mounted on a printed circuit board and programmed using JTAG ...
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... TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD913F1 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Secondary Flash Block. ...
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PSD913F1 Absolute Symbol Maximum T STG Ratings NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent Operating Range Commercial Industrial Commercial Industrial Recommended Symbol Operating Conditions Parameter Storage ...
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... Before calculating the total power consumption, determine the percentage of time that the PSD913F1 is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". The AC power component gives the PLD, Flash memory, EEPROM, and SRAM mA/MHz specification. Figure 28 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. ...
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PSD913F1 AC/DC Figure 28a. PLD I Parameters (cont.) Example of PSD913F1 Typical Power Calculation at V Conditions Highest Composite PLD input frequency MCU ALE frequency (Freq ALE) Operational Modes Number of product terms used Turbo Mode Calculation (typical numbers used) ...
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Preliminary AC/DC Example of Typical Power Calculation at V Parameters Conditions (cont.) Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down ...
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PSD913F1 PSD913F1 DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis ...
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Preliminary Microcontroller AC Symbols for PLD Timing. Interface – Example: AC/DC Parameters Signal Letters (5V ± 10% Versions) A – Address Input C – CEout Output D – Input Data E – E Input L – ALE Input N – ...
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PSD913F1 Microcontroller Interface – PSD913F1 AC/DC Parameters (5V ± 10% Versions) Read Timing (5 V ± 10% Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX t Address Valid ...
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... In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port timing has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. PLD Combinatorial Timing (5 V ± 10%) Symbol ...
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PSD913F1 Microcontroller Interface – PSD913F1 AC/DC Parameters (5V ± 10% Versions) Power Down Timing (5 V ± 10%) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from t APD Enable to Internal CLWH PDN Valid Signal ...
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Preliminary Microcontroller Interface – PSD913F1 AC/DC Parameters (5V ± 10% Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed) WHQV3 t Sector Erase (Not Preprogrammed) ...
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PSD913F1 PSD913F1V DC Characteristics Symbol Parameter V Supply Voltage CC V High Level Input Voltage IH V Low Level Input Voltage IL V Reset High Level Input Voltage IH1 V Reset Low Level Input Voltage IL1 V Reset Pin Hysteresis ...
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Preliminary Microcontroller AC Symbols for PLD Timing. Interface – Example: PSD913F1V AC/DC Signal Letters Parameters A – Address Input C – CEout Output (3 3 – Input Data Versions) E – E Input L – ALE ...
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PSD913F1 Microcontroller Interface – PSD913F1V AC/DC Parameters (3 3.6 V Versions) Read Timing (3 3.6 V Versions) Symbol Parameter t ALE or AS Pulse Width LVLX t Address Setup Time AVLX t Address Hold Time LXAX ...
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... WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. 4. Assuming data is stable before active write signal. 5. Assuming write is active before data becomes valid. 6. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory. PLD Combinatorial Timing (3 3.6 V Versions) ...
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PSD913F1 Microcontroller Interface – PSD913F1V AC/DC Parameters (3 3.6 V Versions) Power Down Timing (3 3.6 V Versions) Symbol Parameter ALE Access Time from t LVDV Power Down Maximum Delay from APD Enable t CLWH to ...
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Preliminary Microcontroller Interface – PSD913F1V AC/DC Parameters (3 3.6 V Versions) Flash Program, Write and Erase Times Symbol Parameter Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t Sector Erase (Preprogrammed) WHQV3 t Sector Erase ...
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PSD913F1 Figure 29. Read Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI RD (PSEN, DS) E R/W t AVPV * t and t are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. ...
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Preliminary Figure 30. Write Timing ALE/AS A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS CSI WR (DS AVLX t LXAX t LVLX ADDRESS VALID t AVWL ADDRESS VALID t SLWL t WLWH t THEH t ...
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PSD913F1 Figure 31. Combinatorial Timing – PLD CPLD INPUT CPLD OUTPUT Figure 32. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO ISCCH t ISCCL t ISCPSU t ISCPH t ISCPZV t ISCPCO t ISCPVZ Preliminary ...
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Preliminary Figure 33. Reset Timing OPERATING LEVEL V CC RESET Figure 34. Key to Switching Waveforms WAVEFORMS t NLNH– OPR POWER ON RESET INPUTS STEADY INPUT MAY CHANGE FROM MAY CHANGE FROM ...
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PSD913F1 Pin Capacitance ° MHz A Symbol OUT C VPP NOTES: 1. These parameters are only sampled and are not 100% tested. Figure 35. AC Testing Input/Output Waveform Figure 36. AC ...
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Preliminary PSD913F1 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) Pin Pin No. Assignments ...
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PSD913F1 PSD913F1 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M) Pin Pin No. Assignments ...
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Preliminary PSD913F1 Figure 37. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC) Package Information Figure 38. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type PD2 PD1 9 10 PD0 ...
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PSD913F1 Figure 37A. Drawing J7 – 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type Family: Plastic Leaded Chip Carrier Symbol Min A 4.19 A1 2.54 A2 3.66 B 0.33 B1 0.66 C 0.246 ...
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Preliminary Figure 38A. Drawing M3 – 52-Pin Plastic Quad Flatpack (PQFP) (Package Type Index 3 Mark B Family: Plastic Quad Flatpack (PQFP) Symbol Min 0° A – A2 1. ...
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... STD-M = Standard MCU interfaces supported (Multiplexed only). PLUS = New Intel 80C251 and Philips 80C51XA supported plus all standard MCUs. w/BB = Battery backed-up SRAM. APD = Automatic Power Down. I/O Memory Ports Flash Program Store JTAG OTP EPROM Boot Parallel ISP EEPROM/EEPROM Boot 2nd Flash Boot SRAM ...
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Preliminary Part Number Construction PSD 413A2 V Ordering Information Part Number PSD913F1-90J PSD913F1-90JI PSD913F1-90M PSD913F1-90MI PSD913F1-12JI PSD913F1-12MI PSD913F1V-15J PSD913F1V-15M PSD913F1V-20JI PSD913F1V-20MI -A - Temperature (Blank = Commercial Industrial Military) Package Type Speed (-70 = ...
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PSD913F1-A REVISION HISTORY Table 1. Document Revision History Date Rev. Aug-2000 1.0 Document written in the WSI format Front page, and back two pages format, added to the PDF file 04-Jan-2002 1.1 References to Waferscale, WSI, EasyFLASH and ...
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