PSD813F1A-12J STMICROELECTRONICS [STMicroelectronics], PSD813F1A-12J Datasheet

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PSD813F1A-12J

Manufacturer Part Number

PSD813F1A-12J

Description

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

Manufacturer

STMICROELECTRONICS [STMicroelectronics]

Datasheet

1.PSD813F1A-12J.pdf (110 pages)

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BOSTOCK HK LIMITED

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PSD813F1A-12JIST10PCS

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FEATURES SUMMARY

August 2004

DUAL BANK FLASH MEMORIES

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–

–

16 Kbit SRAM (BATTERY-BACKED)

PLD WITH MACROCELLS

–

–

–

27 RECONFIGURABLE I/Os

–

ENHANCED JTAG SERIAL PORT

–

–

PAGE REGISTER

–

PROGRAMMABLE POWER MANAGEMENT

1 Mbit of Primary Flash Memory (8

Uniform Sectors)

256 Kbit Secondary EEPROM (4 Uniform

Sectors)

Concurrent operation: read from one

memory while erasing and writing the

other

Over 3,000 Gates Of PLD: DPLD and

CPLD

DPLD - User-defined Internal chip-select

decoding

CPLD with 16 Output Macrocells (OMCs)

and 24 Input Macrocells (IMCs)

27 individually configurable I/O port pins

that can be used for the following

functions:

MCU I/Os;

PLD I/Os;

Latched MCU address output; and

Special function I/Os.

Note: 16 of the I/O ports may be

configured as open-drain outputs.

Built-in JTAG-compliant serial port allows

full-chip In-System Programmability (ISP)

Efficient manufacturing allows for easy

product testing and programming

Internal page register that can be used to

expand the microcontroller address space

by a factor of 256.

Flash In-System Programmable (ISP)

Peripherals for 8-bit MCUs, 5V

Figure 1. Packages

HIGH ENDURANCE:

–

–

–

–

SINGLE SUPPLY VOLTAGE:

–

STANDBY CURRENT AS LOW AS 50µA

100,000 Erase/WRITE Cycles of Flash

Memory

10,000 Erase/WRITE Cycles of EEPROM

1,000 Erase/WRITE Cycles of PLD

Data Retention: 15-year minimum at 90°C

(for Main Flash, Boot, PLD and

Configuration bits).

5V±10% for 5V

TQFQ64 (U)

PQFP52 (M)

PLCC52 (J)

PSD813F1

1/110

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