MT46H8M16LFCF-10 IT Micron Technology Inc, MT46H8M16LFCF-10 IT Datasheet - Page 43

• Manufacturer Part Number: MT46H8M16LFCF-10 IT
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10 IT

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
(auto precharge
(auto precharge
Current State
Row active
disabled)
disabled)
Write
Read
Any
Idle
Truth Table – Current State Bank n - Command to Bank n
Notes: 1–6; notes appear below and on next page
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. COM-
1. This table applies when CKE
RAS#
the previous state was self refresh) and after
power-down).
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
MAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 10, and according to Table 11.
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
precharge enabled:
precharge enabled:
CAS#
Row activating: Starts with registration of an ACTIVE command and ends when
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
Write w/auto-
Read w/auto-
Precharging: Starts with registration of a PRECHARGE command and ends when
Row active: A row in the bank has been activated, and
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Write: A WRITE burst has been initiated, with auto precharge disabled,
Read: A READ burst has been initiated, with auto precharge disabled,
Idle: The bank has been precharged, and
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
data bursts/accesses and no register accesses are in progress.
and has not yet terminated or been terminated.
and has not yet terminated or been terminated.
t
t
state.
Starts with registration of a READ command with auto precharge
enabled and ends when
bank will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
bank will be in the idle state.
RP is met. Once
RCD is met. Once
n-1
43
was HIGH and CKE
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command/Action
t
RP is met, the bank will be in the idle state.
t
RCD is met, the bank will be in the row active
t
PDX has been met (if the previous state was
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH and after
t
RP has been met.
©2006 Micron Technology, Inc. All rights reserved.
t
RCD has been met. No
t
XSR has been met (if
t
t
RP is met, the
RP is met, the
Truth Tables
Notes
Advance
10, 12
10, 11
8, 11
10
10
10
10
7
7
8
8
9