PSD834F2-90J STMicroelectronics, PSD834F2-90J Datasheet - Page 65

• Manufacturer Part Number: PSD834F2-90J
• Description: IC FLASH 2MBIT 90NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-90J

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2006-5

Table 30. Power Management Mode Registers PMMR0 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Table 31. Power Management Mode Registers PMMR2 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
X
APD Enable
X
PLD Turbo
PLD Array clk
PLD MCell clk
X
X
X
X
PLD Array
CNTL0
PLD Array
CNTL1
PLD Array
CNTL2
PLD Array
ALE
PLD Array
DBE
X
0
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
0
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
0 = on
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
0
0
0
0
0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
0
Not used, and should be set to zero.
Not used, and should be set to zero.
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is ’0.’
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Doc ID 10552 Rev 3
PSD813F2V, PSD854F2V
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