PSD834F2-90J STMicroelectronics, PSD834F2-90J Datasheet - Page 25

• Manufacturer Part Number: PSD834F2-90J
• Description: IC FLASH 2MBIT 90NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD834F2-90J

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2006-5

PROGRAMMING FLASH MEMORY
Flash memory must be erased prior to being pro-
grammed. A byte of Flash memory is erased to all
1s (FFh), and is programmed by setting selected
bits to ’0.’ The MCU may erase Flash memory all
at once or by-sector, but not byte-by-byte. Howev-
er, the MCU may program Flash memory byte-by-
byte.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
byte or to erase sectors (see
Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PC3).
Data Polling
Polling on the Data Polling Flag Bit (DQ7) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure
shows the Data Polling algorithm.
When the MCU issues a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the byte to be pro-
grammed in Flash memory to check status. The
Data Polling Flag Bit (DQ7) of this location be-
comes the complement of b7 of the original data
byte to be programmed. The MCU continues to
poll this location, comparing the Data Polling Flag
Bit (DQ7) and monitoring the Error Flag Bit (DQ5).
When the Data Polling Flag Bit (DQ7) matches b7
of the original data, and the Error Flag Bit (DQ5)
remains ’0,’ the embedded algorithm is complete.
If the Error Flag Bit (DQ5) is '1,' the MCU should
test the Data Polling Flag Bit (DQ7) again since
the Data Polling Flag Bit (DQ7) may have changed
simultaneously with the Error Flag Bit (DQ5, see
Figure 7).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read
the location again after the embedded program-
Table 9., page
Doc ID 10552 Rev 3
21).
7
ming algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure
Data Polling Flag Bit (DQ7) is '0' until the Erase cy-
cle is complete. A 1 on the Error Flag Bit (DQ5) in-
dicates a time-out condition on the Erase cycle; a
0 indicates no error. The MCU can read any loca-
tion within the sector being erased to get the Data
Polling Flag Bit (DQ7) and the Error Flag Bit
(DQ5).
PSDsoft Express generates ANSI C code func-
tions which implement these Data Polling algo-
rithms.
Figure 7. Data Polling Flowchart
at VALID ADDRESS
NO
READ DQ5 & DQ7
READ DQ7
START
PSD813F2V, PSD854F2V
DATA
DATA
DQ7
DQ5
DQ7
FAIL
7
= 1
=
=
still applies. However, the
YES
NO
NO
YES
YES
PASS
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