IDT7130LA55P IDT, Integrated Device Technology Inc, IDT7130LA55P Datasheet
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IDT7130LA55P
Specifications of IDT7130LA55P
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IDT7130LA55P Summary of contents
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... Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin PLCC, and 64-pin STQFP and TQFP Green parts available, see ordering information I/O I/O Control Control MEMORY ARRAY 10 ARBITRATION and INTERRUPT LOGIC 1 IDT7130SA/LA ...
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... Both devices provide two independent ports with separate con- trol, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry Pin Configurations ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Pin Configurations (1,2,3) 01/08/02 INDEX I/O 0L I/O 1L I/O 2L I/O ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias Storage -65 ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (Both Ports Active) ( ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Data Retention Characteristics Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t Operation Recovery ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775Ω Figure 1. Output Test Load 5V BUSY or ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and is OE ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter WRITE CYCLE (3) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing) ADDRESS R/W (4) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2, (CE ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER IDT 7130) BUSY Access Time from Address t BAA BUSY Disable Time from Address ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" "A " DATA IN"A" (1) t APS ADDR "B" BUSY "B" DATA OUT"B" NOTES ensure ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR AND 'A' 'B' CE 'B' (2) t APS CE 'A' BUSY 'A' Timing Waveform by BUSY Arbitration Controlled by Address ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t ...
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... LOW regardless of actual logic level on R the pin. Military, Industrial and Commercial Temperature Ranges Port Disabled and in Power-Down Mode Power-Down Mode (2) Data on Port Written into Memory IN (3) Data in Memory Output on Port OUT High Impedance Outputs timing. DDD (1,4) Right Port INT CE R ...
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... R memory location 3FF (HEX) and to clear the interrupt flag (INT right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Ordering Information XXXX A 999 Device Type Power Speed Package NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts ...
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IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Datasheet Document History (cont'd) 01/08/02: Page 5, 8, 10, 12, & 14 Page 5, 8, 10, 12, & 14 Page 18 Page 1 & 19 01/11/06: Page 1 Page 18 ...