IDT7130LA55P IDT, Integrated Device Technology Inc, IDT7130LA55P Datasheet - Page 16
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IDT7130LA55P
Manufacturer Part Number
IDT7130LA55P
Description
IC SRAM 8KBIT 55NS 48DIP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT7140LA25JGI.pdf
(19 pages)
Specifications of IDT7130LA55P
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
8K (1K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
7130LA55P
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT7130LA55P
Manufacturer:
WB
Quantity:
1 440
Part Number:
IDT7130LA55P
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT7130LA55PF
Manufacturer:
IDT
Quantity:
9
Company:
Part Number:
IDT7130LA55PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT7130LA55PF
Manufacturer:
IDT
Quantity:
20 000
Truth Tables
Truth Table I — Non-Contention Read/Write Control
NOTES:
1. A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
4. 'H' = V
Truth Table II — Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Truth Table III — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
3. Writes to the left port are internally ignored when BUSY
CE
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
X
X
H
L
R/W
IDT7140 (slave). BUSY
outputs. On slaves the BUSY
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
result. BUSY
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSY
the pin.
R/W
L
0L
X
X
L
H
H
X
X
X
L
– A
L
IH
CE
10L
L
R
, 'L' = V
X
X
H
L
= V
R
= V
Inputs
L
• A
and BUSY
L
IL
IL
CE
CE
0R
and BUSY
, then No Change.
, then No Change.
H
H
X
X
L
L
L
L
L
IL
L
NO MATCH
L
– A
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
= BUSY
A
A
MATCH
MATCH
MATCH
0R
0L
Inputs
R
10R
-A
-A
outputs are driving LOW regardless of actual logic level on
R
X
.
9L
9R
are both outputs for IDT7130 (master). Both are inputs for
R
outputs on the IDT7130 are open drain, not push-pull
Left Port
R
outputs can not be LOW simultaneously.
OE
(1)
OE
= V
X
X
X
H
X
X
X
L
L
APS
X
L
input internally inhibits writes.
IH
is not met, either BUSY
BUSY
(2)
H
H
H
DATA
A
WDD
L
DATA
9L
3FE
Outputs
(1)
3FF
D
X
X
-A
Z
Z
Z
0-7
and t
0L
OUT
IN
BUSY
DDD
(2)
H
H
H
Port Disabled and in Power-Down Mode, I
Data on Port Written into Memory
Data in Memory Output on Port
High Impedance Outputs
CE
R
L
timing.
INT
(1)
outputs are driving LOW
L
X
X
H
R
L
or BUSY
(3)
(2)
L
= CE
Write Inhibit
Function
L
Normal
Normal
Normal
R
= V
R/W
= LOW will
(1,4)
X
X
X
2689 tbl 15
L
IH
, Power-Down Mode, I
R
(3)
16
CE
X
X
L
L
R
(3)
Military, Industrial and Commercial Temperature Ranges
(2)
Right Port
OE
X
X
X
L
SB1
R
SB2
or I
or I
Function
SB3
SB4
A
9R
3FF
3FE
X
X
-A
0R
(4)
INT
X
X
H
L
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Function
L
R
Flag
L
Flag
R
Flag
Flag
2689 tbl 13
2689 tbl 14