N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 34

• Manufacturer Part Number: N25Q128A13BSF40F
• Description: IC SRL FLASH 128MB NMX 16-SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BSF40F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Volatile and Non Volatile Registers
6.1.5
6.2
34/157
The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0)
bits to determine if the protected area defined by the Block Protect bits starts from the top or
the bottom of the memory array:
The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect
(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status
Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In
this mode, the non-volatile bits of the Status Register (TB, BP3, BP2, BP1, BP0) become
read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for
execution.
Non Volatile Configuration Register
The Non Volatile Configuration Register (NVCR) bits affects the default memory
configuration after power-on. It can be used to make the memory start in the configuration to
fit the application requirements.
The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1
(FFFFh).
The purpose of the NVCR is to define the default memory settings after the power-on
sequence related to many features:
The NVCR can be read by the Read Non Volatile Configuration Register (RDNVCR)
instruction and written by the Write Non Volatile Configuration Register (WRNVCR) in all the
3 available SPI protocols. See the sections that follow as well as
Configuration
When TB is reset to '0' (default value), the area protected by the Block Protect bits
starts from the top of the memory array.
When TB is set to '1', the area protected by the Block Protect bits starts from the bottom
of the memory array.
The number of dummy clock cycle for fast read instructions,
XIP mode configurations,
output driver strengths,
Reset (or Hold) disabling
Multiple I/O protocol enabling.
Register.
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Table 3.: Non-Volatile
N25Q128 - 3 V